diff options
| author | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
| commit | 3e38691e8f7aa0d9b498d76c7279ddec6e4946f3 (patch) | |
| tree | bec2e661298847dc5bcf9335ef31259686e882e1 /cpu/mips/start.S | |
| parent | 36c05a80ecbe3997abd9aa628a68dd6c0bacf681 (diff) | |
* Patch by Arun Dharankar, 4 Apr 2003:LABEL_2003_04_05_0300
Add IDMA example code (tested on 8260 only)
* Add support for Purple Board (MIPS64 5Kc)
* Add support for MIPS64 5Kc CPUs
* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
* Patch by Denis Peter, 04 Apr 2003:
- update MIP405-4 board
* Patches by Denis Peter, 03 April 2003:
- fix PCI IRQs on MPL boards
- fix two more un-relocated pointer problems
* Fix behaviour of "run" command:
- print error message iv variable does not exist
- terminate processing of arguments in case of error
* Patches by Peter Figuli, 10 Mar 2003
- Add support for BTUART on PXA platform
- Add support for WEP EP250 (PXA) board
* Fix flash problems on INCA-IP; add tool to allow bruning images to
flash using a BDI2000
* Implement fix for I2C Edge Conditions problem for all boards that
use the bit-banging driver (common/soft_i2c.c)
* Add patches by Robert Schwebel, 31 Mar 2003:
- csb226 board: bring in sync with innokom/memsetup.S
- csb226 board: fix MDREFR handling
- misc doc fixes / extensions
- innokom board: cleanup, MDREFR fix in memsetup.S, config update
- add BOOT_PROGRESS to armlinux.c
Diffstat (limited to 'cpu/mips/start.S')
| -rw-r--r-- | cpu/mips/start.S | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/cpu/mips/start.S b/cpu/mips/start.S index bf116556175..86a8407f61a 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -42,9 +42,12 @@ _start: RVECENT(reset,0) /* U-boot entry point */ RVECENT(reset,1) /* software reboot */ -#ifdef CONFIG_INCA_IP - .word 0x000020C4 /* EBU init code, fetched during booting */ - .word 0x00000000 /* phase of the flash */ +#if defined(CONFIG_INCA_IP) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word 0x00000000 /* phase of the flash */ +#elif defined(CONFIG_PURPLE) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ #else RVECENT(romReserved,2) #endif @@ -178,6 +181,30 @@ _start: * 128 * 8 == 1024 == 0x400 * so this is address R_VEC+0x400 == 0xbfc00400 */ +#ifdef CONFIG_PURPLE +/* 0xbfc00400 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +/* 0xbfc00428 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +#endif /* CONFIG_PURPLE */ .align 4 reset: @@ -283,12 +310,17 @@ relocate_code: * t1 = target address * t2 = source end address */ + /* On the purple board we copy the code earlier in a special way + * in order to solve flash problems + */ +#ifndef CONFIG_PURPLE 1: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b addu t1, 4 /* delay slot */ +#endif /* If caches were enabled, we would have to flush them here. */ |