diff options
author | Dirk Behme <dirk.behme@googlemail.com> | 2008-12-14 09:47:14 +0100 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-01-24 17:51:21 +0100 |
commit | 5ed3e8659e5373f6a229877ac506c0b00a054fb8 (patch) | |
tree | a64fe24e92df472fd0e442077230e6004e7a9260 /cpu/arm_cortexa8/omap3/syslib.c | |
parent | 0b02b184003e6a5023e05d5f31de54db279b1431 (diff) |
OMAP3: Add common clock, memory and low level code
Add common clock, memory and low level code
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Diffstat (limited to 'cpu/arm_cortexa8/omap3/syslib.c')
-rw-r--r-- | cpu/arm_cortexa8/omap3/syslib.c | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/omap3/syslib.c b/cpu/arm_cortexa8/omap3/syslib.c new file mode 100644 index 00000000000..9ced495c8d0 --- /dev/null +++ b/cpu/arm_cortexa8/omap3/syslib.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = readl((u32)addr) & ~(msk << start_bit); + tmp |= value << start_bit; + writel(tmp, (u32)addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = readl((u32)read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} |