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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-06-08 18:02:32 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-06-09 08:19:13 +0900
commit9c2f9b2da650907b928995350cc4e29480fb0f80 (patch)
tree5c020419fa8e0c2977c1e45c117924a229bafc75 /configs
parentf7e9402b54db4bed916c9adb2565d9713ca5bbfa (diff)
ARM: uniphier: insert dsb barrier to ensure visibility of store
I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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