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authorStefan Roese <sr@denx.de>2019-05-23 07:55:54 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2019-05-24 15:55:17 +0200
commitf913eab9b95c01c96b9e17eba853a99eb8ddb41a (patch)
treeb882dbe8c550e3a4c961fc43dd9ed52e0be20a13 /configs/gardena-smart-gateway-mt7688-ram_defconfig
parent49901cc185b721734430d6b7dff649dcb6ee8cff (diff)
mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INIT
With commit 06985289d452 ("watchdog: Implement generic watchdog_reset() version") the init sequence has changed in arch_misc_init(), resulting in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena). When this happens, the first (or sometimes later ones as well) TFTP command hangs and does not complete correctly. This leads to the assumption that the d-cache is not in a clean state once the ethernet driver is called (d-cache is used here for the buffers). The old work- around with the cache flush somehow does not work any more now with the new code change. To fix this issue, this patch now removes the old workaround and selects CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the complete malloc area is initialized with zeros (cache lines are touched). Testing has shown that this also fixes the issue on the MT7688 boards. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'configs/gardena-smart-gateway-mt7688-ram_defconfig')
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