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authorIcenowy Zheng <icenowy@aosc.xyz>2017-04-08 15:30:14 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-21 09:29:35 +0200
commitf02abb0608fe7e47fa1ee62e0f7655d7e0e53a12 (patch)
tree414da6c4e6816d95a85d8a20370deb1073c1a993 /configs/LicheePi_Zero_defconfig
parente267d94011cde1d841106d0b6505dbd63f57d944 (diff)
sunxi: add support for Lichee Pi Zero
Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'configs/LicheePi_Zero_defconfig')
-rw-r--r--configs/LicheePi_Zero_defconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
new file mode 100644
index 00000000000..c1470848495
--- /dev/null
+++ b/configs/LicheePi_Zero_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_V3S=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=14779
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_NETDEVICES is not set