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authorEugen Hristev <eugen.hristev@microchip.com>2019-05-24 09:38:10 +0300
committerEugen Hristev <eugen.hristev@microchip.com>2019-06-06 10:56:42 +0300
commit0be07872e3200d9d0f6829e641166f0781327cdf (patch)
treedd1d60c2046521f7a1067da5b1fe623e8e763a05 /common
parentcd60ea71f380ee4c7af2a56419d6234878b950e4 (diff)
spl: at91: add support for SPL_AT91_MCK_BYPASS
By default the configuration of the PMC is to have an external crystal connected that requires driving on both XIN and XOUT pins. The bypass configuration means that only XIN will be used, the SoC will not do any driving, and the XIN needs to be provided with a proper signal. This is the MOSCXTBY bit in the PMC main clock generator register. The SPL needs to properly initialize the PMC registers before switching to external clock signal and raising the clock to the cruise speed. Also created Kconfig for this specific configuration. By default this is disabled. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Diffstat (limited to 'common')
-rw-r--r--common/spl/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dd078fe79d1..0d01353ee84 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1151,5 +1151,17 @@ config TPL_YMODEM_SUPPORT
endif # TPL
+config SPL_AT91_MCK_BYPASS
+ bool "Use external clock signal as a source of main clock for AT91 platforms"
+ depends on ARCH_AT91
+ default n
+ help
+ Use external 8 to 24 Mhz clock signal as source of main clock instead
+ of an external crystal oscillator.
+ This option disables the internal driving on the XOUT pin.
+ The external source has to provide a stable clock on the XIN pin.
+ If this option is disabled, the SoC expects a crystal oscillator
+ that needs driving on both XIN and XOUT lines.
+
endif # SPL
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