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author | Kautuk Consul <kconsul@ventanamicro.com> | 2022-12-07 17:12:35 +0530 |
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committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-12-08 15:15:58 +0800 |
commit | ae3527f088062dc4e117b0c4d4319e068f5e44cd (patch) | |
tree | fa08dd5ee80ff563cb71240bafd1ad0b23ff22cd /common | |
parent | 1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 (diff) |
arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'common')
0 files changed, 0 insertions, 0 deletions