diff options
| author | Matt Ranostay <mranostay@ti.com> | 2022-07-26 01:36:09 -0700 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-07-28 17:24:49 -0500 |
| commit | fe0c9443216af5854477a17693cb74a3653a92df (patch) | |
| tree | 078e1f49254708c265e6f865b14608d457b70e05 /common | |
| parent | 3f031bb1baad799bec97f36ca12ca74fd7c79b05 (diff) | |
spl: Add support for enabling d-cache in board_init_r
This patchset reimplements part of the dropped patchset bd236384ceef
which enables d-cache during SPL execution.
Having the d-cache disabled created a regression that added additional
250 milliseconds to A72 SPL boot time on the J721E platform.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Diffstat (limited to 'common')
| -rw-r--r-- | common/spl/spl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/common/spl/spl.c b/common/spl/spl.c index 63c48fbf33..ce0319852e 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -31,6 +31,7 @@ #include <fdt_support.h> #include <bootcount.h> #include <wdt.h> +#include <cpu_func.h> DECLARE_GLOBAL_DATA_PTR; @@ -602,6 +603,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_set_bd(); +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ + (defined(CONFIG_CPU_V7A) || defined(CONFIG_ARM64) || \ + defined(CONFIG_CPU_V7R)) + enable_caches(); +#endif + #if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); |