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authorRajashekhara, Sudhakar <sudhakar.raj@ti.com>2012-07-10 13:41:46 +0530
committerRajashekhara, Sudhakar <sudhakar.raj@ti.com>2012-07-10 13:41:46 +0530
commit67ae04a9d961d03e98241de7105f2c5a5f445732 (patch)
treef30af3a470aecb47c702a9cab965422552fd99a3 /common
parent269d186ab8eb3ad22d4fa89b159d02c060b95be7 (diff)
da850/omapl138: configure pll1_sysclk3 within allowable limits2012.04-davinci-ts1
Currently PLL1_SYSCLK3 clock is being configured to 88MHz but the latest OMAP-L138 data sheet (http://www.ti.com/lit/ds/symlink/omap-l138.pdf) restricts this frequency to maximum of 75MHz. This patch modifies the PLL divider and configures PLL1_SYSCLK3 to 66MHz. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
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