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authorJim Lin <jilin@nvidia.com>2011-02-24 11:10:06 -0800
committerSimon Glass <sjg@chromium.org>2011-08-24 09:56:46 -0700
commit0d5ff952e7c3fc800a6234b5f1b5b94391d0bd39 (patch)
tree8662dbba9464c0dff7d6c22d6797734dd4a752a3 /common/usb.c
parent65bc17b32ce0906ff4d9cc5560b45269545a202c (diff)
Chromium: arm: tegra: seaboard: Fix issue that USB device on USB1 port is not detected.
BUG=Chrome-os-partner:2287 TEST=Attached USB high-speed or low-speed device to USB1 port and ran "usb reset 1" in command line. Device could be detected successfully. Signed-off-by: Jim Lin <jilin@nvidia.com> 1. Power of USB1 is enabled by USB1_VBUS_EN which is an output pin of SDIO3_DAT5 on Seaboard platform. Pad SDIO3_DAT5 belongs to pinmux group SLXK. It is initialized in board_usb_init function of board/tegra2/common/board.c but its state is changed to tri-state later in gpinit(). This is not right. So first fix is to remove setting of SLXK in tegra2_gp_pinmux table of gpinit.c. 2. USB1 port may need 2 Port Reset events to make Port Enable bit to be set in PORTSC register. The fix is to make running path to retry. Review URL: http://codereview.chromium.org/6542040 Patch from Jim Lin <jilin@nvidia.com>. Change-Id: I486b5196e54ef3a7fa21fd309eb619666c01bc8a Reviewed-on: http://gerrit.chromium.org/gerrit/398 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'common/usb.c')
-rw-r--r--common/usb.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/common/usb.c b/common/usb.c
index f8c1d70ea8f..8afe5875774 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1171,6 +1171,14 @@ static int hub_port_reset(struct usb_device *dev, int port,
/* we have finished trying to reset, so return */
usb_clear_port_feature(dev,
port + 1, USB_PORT_FEAT_C_RESET);
+#ifdef CONFIG_TEGRA2
+ /* Sometimes Port Enable bit is not set in PORTSC
+ * register after a Port Reset, we need another Port
+ * Reset to make it set.
+ */
+ if (status)
+ break;
+#endif
return 0;
}