summaryrefslogtreecommitdiff
path: root/boot
diff options
context:
space:
mode:
authorAndrejs Cainikovs <andrejs.cainikovs@toradex.com>2023-08-08 12:21:25 +0200
committerAndrejs Cainikovs <andrejs.cainikovs@toradex.com>2023-09-12 15:16:30 +0000
commit3702ee4936c0250550a7022e076384e196c86d01 (patch)
tree1be601ab1874927e4cc665295a5eb0c525bcc97e /boot
parent01272a9f2a8c72a7f4e908c05f1588699160d5a8 (diff)
board: toradex: verdin-imx8mm: set fixed LPDDR4 refresh rate as per errata ERR050805
Update lpddr4 configuration and training using updated spreadsheet and tools from NXP using data from previous spreadsheet and verified toward datasheet: - MX8M_Mini_LPDDR4_RPA_v22.xlsx - mscale_ddr_tool_v3.31_setup.exe The most relevant update is related to errata ERR050805: "DRAM: Controller automatic derating logic may not work when the LPDDR4 memory temperature is above 85 °C at initialization" Other relevant fixes: - DRAMTMG7 register: corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4) - RANKCTL register: corrected calculations for ODTLon and ODTLoff to follow the JEDEC specification - ADDRMAP7 register: added support for 17-row devices As per errata ERR050805: An issue exists with the automatic derating logic of the DDR controller that only samples the LPDDR4 MR4 register when the Temperature Update Flag (TUF) field (MR4[7] ) is 1’b1. If the LPDDR4 memory is initialized and starts operation above 85 °C (MR4[2:0] > 3’b011), the MR4 Temperature Update Flag (TUF) will not be set. The DDR Controller will therefore not automatically adjust the memory refresh rate or de-rate memory timings based on the LPDDR4 memory temperature. This may cause the controller incorrectly setting the refresh period, potentially cause the LPDDR4 memory losing data contents and lead to possible data integrity issues above 85 °C. Errata provides three possible workaround options, while option 2 is the most reasonable: Disable the automatic derating logic of the DDR controller and apply fixed x2 refresh rate (0.5x refresh). This option is suitable for designs that are expected to boot at or above 85 °C and memory’s MR4[2:0] (Refresh Rate) DOES NOT report the following conditions: 3b101: 0.25x refresh, no de-rating 3b110: 0.25x refresh, with de-rating 3b111: SDRAM High temperature operating limit exceeded [1]: https://www.nxp.com/docs/en/errata/IMX8MM_0N87W.pdf Upstream-Status: Pending Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Diffstat (limited to 'boot')
0 files changed, 0 insertions, 0 deletions