Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Conflicts:
	drivers/serial/Makefile

15 files changed, 951 insertions, 4 deletions

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index e155556ce2..8f0f9b8de2 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -336,7 +336,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile
new file mode 100644
index 0000000000..ac16c1fe3f
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := cgtqmx6eval.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README
new file mode 100644
index 0000000000..bbf0f75a4d
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/README
@@ -0,0 +1,29 @@
+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
+qmx6 quad module.
+
+This file contains information for the port of U-Boot to the Congatec
+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+This version of u-boot works only on the SD card. By default, the
+Congatec board can boot only from the SPI-NOR.
+But, with the u-boot version provided with the board you can write boot
+registers to force the board to reboot and boot from the SD slot. If
+"bmode" command is not available from your pre-installed u-boot, these
+instruction will produce the same effect:
+
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
+conga-QMX6 U-Boot > reset
+resetting ...
+
+The the board will reboot and, if you have written your SD correctly
+the board will use u-boot that live into the SD
+
+To copy the resulting u-boot.imx to the SD card:
+
+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
+
+Note: Replace xxx with the device representing the SD card in your system.
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
new file mode 100644
index 0000000000..f70f674b21
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on mx6qsabrelite.c file
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(1, 4));
+		ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+		break;
+	case USDHC4_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+		break;
+	default:
+		printf("Bad USDHC interface\n");
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+	status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+		     fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Conga-QEVAL QMX6 Quad\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
index 41ba303ec4..d25e2b37ce 100644
--- a/board/freescale/mx23evk/mx23evk.c
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -43,6 +43,12 @@ int board_early_init_f(void)
 	/* SSP0 clock at 96MHz */
 	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 
+	/* Power on LCD */
+	gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
index 6be8c8d9d0..fd71f7dc1b 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -27,6 +27,7 @@
 
 #define	MUX_CONFIG_SSP1	(MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_4MA | MXS_PAD_NOPULL)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
@@ -96,6 +97,37 @@ const iomux_cfg_t iomux_setup[] = {
 	/* Slot Power Enable */
 	MX23_PAD_PWM3__GPIO_1_29 |
 		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* LCD */
+	MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
+	MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
 };
 
 #define HW_DRAM_CTL14	(0x38 >> 2)
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index ae6eda343e..beae0e66e2 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -30,6 +30,7 @@
 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
@@ -162,6 +163,38 @@ const iomux_cfg_t iomux_setup[] = {
 	/* I2C */
 	MX28_PAD_I2C0_SCL__I2C0_SCL,
 	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* LCD */
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
+	MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
 };
 
 #define HW_DRAM_CTL29	(0x74 >> 2)
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index de7231bd10..4edd9f4193 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -59,6 +59,12 @@ int board_early_init_f(void)
 	gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
 #endif
 
+	/* Power on LCD */
+	gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index bfe4868e8a..2a6e3a9192 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -26,12 +26,14 @@
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,6 +48,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -76,6 +84,45 @@ iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+iomux_v3_cfg_t const i2c3_pads[] = {
+	MX6_PAD_EIM_A24__GPIO_5_4		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const port_exp[] = {
+	MX6_PAD_SD2_DAT0__GPIO_1_15		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static void setup_iomux_enet(void)
 {
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@@ -216,6 +263,16 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	/* I2C 3 Steer */
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 8ce054e428..862bc3099d 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -308,7 +308,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile
new file mode 100644
index 0000000000..74162281ae
--- /dev/null
+++ b/board/freescale/vf610twr/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 0000000000..b00d4c1cd3
--- /dev/null
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 0000000000..f14df8b6e1
--- /dev/null
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A14__DDR_A_14,
+		VF610_PAD_DDR_A13__DDR_A_13,
+		VF610_PAD_DDR_A12__DDR_A_12,
+		VF610_PAD_DDR_A11__DDR_A_11,
+		VF610_PAD_DDR_A10__DDR_A_10,
+		VF610_PAD_DDR_A9__DDR_A_9,
+		VF610_PAD_DDR_A8__DDR_A_8,
+		VF610_PAD_DDR_A7__DDR_A_7,
+		VF610_PAD_DDR_A6__DDR_A_6,
+		VF610_PAD_DDR_A5__DDR_A_5,
+		VF610_PAD_DDR_A4__DDR_A_4,
+		VF610_PAD_DDR_A3__DDR_A_3,
+		VF610_PAD_DDR_A2__DDR_A_2,
+		VF610_PAD_DDR_A1__DDR_A_1,
+		VF610_PAD_DDR_BA2__DDR_BA_2,
+		VF610_PAD_DDR_BA1__DDR_BA_1,
+		VF610_PAD_DDR_BA0__DDR_BA_0,
+		VF610_PAD_DDR_CAS__DDR_CAS_B,
+		VF610_PAD_DDR_CKE__DDR_CKE_0,
+		VF610_PAD_DDR_CLK__DDR_CLK_0,
+		VF610_PAD_DDR_CS__DDR_CS_B_0,
+		VF610_PAD_DDR_D15__DDR_D_15,
+		VF610_PAD_DDR_D14__DDR_D_14,
+		VF610_PAD_DDR_D13__DDR_D_13,
+		VF610_PAD_DDR_D12__DDR_D_12,
+		VF610_PAD_DDR_D11__DDR_D_11,
+		VF610_PAD_DDR_D10__DDR_D_10,
+		VF610_PAD_DDR_D9__DDR_D_9,
+		VF610_PAD_DDR_D8__DDR_D_8,
+		VF610_PAD_DDR_D7__DDR_D_7,
+		VF610_PAD_DDR_D6__DDR_D_6,
+		VF610_PAD_DDR_D5__DDR_D_5,
+		VF610_PAD_DDR_D4__DDR_D_4,
+		VF610_PAD_DDR_D3__DDR_D_3,
+		VF610_PAD_DDR_D2__DDR_D_2,
+		VF610_PAD_DDR_D1__DDR_D_1,
+		VF610_PAD_DDR_D0__DDR_D_0,
+		VF610_PAD_DDR_DQM1__DDR_DQM_1,
+		VF610_PAD_DDR_DQM0__DDR_DQM_0,
+		VF610_PAD_DDR_DQS1__DDR_DQS_1,
+		VF610_PAD_DDR_DQS0__DDR_DQS_0,
+		VF610_PAD_DDR_RAS__DDR_RAS_B,
+		VF610_PAD_DDR_WE__DDR_WE_B,
+		VF610_PAD_DDR_ODT1__DDR_ODT_0,
+		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+		&ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+		DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+		&ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+		DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+		&ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+		DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+		&ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+		&ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+	writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+	writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+	writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+		&ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+		&ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+		&ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+		&ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+		&ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+		&ddrmr->cr[132]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+		&ddrmr->cr[139]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+		&ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+	ddr_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	udelay(200);
+}
+
+int dram_init(void)
+{
+	setup_iomux_ddr();
+
+	ddr_ctrl_init();
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	static const iomux_v3_cfg_t enet0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t esdhc1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+		CCM_CCGR0_UART1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+		CCM_CCGR3_ANADIG_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+		CCM_CCGR4_GPC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+		CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+		CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+		CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+		CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: vf610twr\n");
+
+	return 0;
+}
diff --git a/board/wandboard/README b/board/wandboard/README
index e0b0b33020..ce83bbe4c5 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -14,12 +14,12 @@ Building U-boot for Wandboard
 
 To build U-Boot for the Wandboard Dual Lite version:
 
-$ make wanboard_dl_config
+$ make wandboard_dl_config
 $ make
 
 To build U-Boot for the Wandboard Solo version:
 
-$ make wanboard_solo_config
+$ make wandboard_solo_config
 $ make
 
 Flashing U-boot into the SD card
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index bb983528b9..5666cbf26f 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -10,9 +10,11 @@
  */
 
 #include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -21,9 +23,11 @@
 #include <asm/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <ipu_pixfmt.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <linux/fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -206,6 +210,88 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(void)
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+static struct fb_videomode const hdmi = {
+	.name           = "HDMI",
+	.refresh        = 60,
+	.xres           = 1024,
+	.yres           = 768,
+	.pixclock       = 15385,
+	.left_margin    = 220,
+	.right_margin   = 40,
+	.upper_margin   = 21,
+	.lower_margin   = 7,
+	.hsync_len      = 60,
+	.vsync_len      = 10,
+	.sync           = FB_SYNC_EXT,
+	.vmode          = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+	int ret;
+
+	ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+
+	if (ret)
+		printf("HDMI cannot be configured: %d\n", ret);
+
+	enable_hdmi();
+
+	return ret;
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on IPU clock */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+		| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+
+	/* clear HDMI PHY reset */
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+		| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+		| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+	      | (CHSCCDR_PODF_DIVIDE_BY_3
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+	      | (CHSCCDR_IPU_PRE_CLK_540M_PFD
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
 int board_eth_init(bd_t *bis)
 {
 	int ret;
@@ -222,9 +308,21 @@ int board_eth_init(bd_t *bis)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
 	return 0;
 }
 
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */