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authorSimon Glass <sjg@chromium.org>2011-11-29 17:20:22 -0800
committerGerrit <chrome-bot@google.com>2011-12-05 11:55:05 -0800
commit23ef5fa2a6ae8f6c76524fd441a4bcbe385533ca (patch)
tree7bad5e0ee1a8bc910a97f04e4bcfd2b16f609ff3 /board
parent28baa5606172c45730b507f4c6047718f7a85d6b (diff)
tegra: Add a clock rate parameter to clock_early_init()
Since PLLP can be set to two different values, make it a parameter to the function that sets up the PLLs. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d Reviewed-on: https://gerrit.chromium.org/gerrit/12245 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board')
-rw-r--r--board/nvidia/common/board.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 599d082e4dc..89f6303625f 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -337,6 +337,7 @@ int board_init(void)
int board_early_init_f(void)
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
+ ulong pllp_rate = 216000000; /* default PLLP clock rate */
#ifdef CONFIG_OF_CONTROL
struct fdt_uart uart;
@@ -356,7 +357,10 @@ int board_early_init_f(void)
#endif /* CONFIG_OF_CONTROL */
/* Initialize essential common plls */
- clock_early_init();
+#ifdef CONFIG_OF_CONTROL
+ pllp_rate = fdt_decode_clock_rate(gd->blob, "pllp", pllp_rate);
+#endif
+ clock_early_init(pllp_rate);
/* Initialize UART clocks */
clock_init_uart(uart_ids);