diff options
| author | Bryan Brattlof <bb@ti.com> | 2023-11-07 17:30:40 -0600 |
|---|---|---|
| committer | Praneeth Bajjuri <praneeth@ti.com> | 2023-11-07 17:55:03 -0600 |
| commit | dee6f6f1c2c12d069dcfc4b0f480092db199316a (patch) | |
| tree | bb0538c57db35d2ac9e4e741a9a57532a18ad312 /board | |
| parent | 851aa09d1e18ce79b7527b059f3f4003a661c341 (diff) | |
board: ti: am62x: remove rtc setup from spl_board_init()
The am62xxx extended family uses the same 32k crystal for all of its
starter kits. Move this to the common board directory to avoid repeating
this everywhere.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/am62x/evm.c | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 4c95622eda..60cc05f27a 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -126,13 +126,6 @@ static int video_setup(void) #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 -#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 -#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 -#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c -#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 -#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 -#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 - void spl_board_init(void) { u32 val; @@ -147,29 +140,6 @@ void spl_board_init(void) val &= ~(CORE_VOLTAGE); writel(val, CTRLMMR_USB1_PHY_CTRL); - /* We have 32k crystal, so lets enable it */ - val = readl(MCU_CTRL_LFXOSC_CTRL); - val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); - writel(val, MCU_CTRL_LFXOSC_CTRL); - /* Add any TRIM needed for the crystal here.. */ - /* Make sure to mux up to take the SoC 32k from the crystal */ - writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, - MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); - - /* Setup debounce conf registers - arbitrary values. Times are approx */ - /* 1.9ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); - /* 5ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); - /* 20ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); - /* 46ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); - /* 100ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); - /* 156ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); - video_setup(); enable_caches(); if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP)) |