board: verdin-am62: set cpu core voltage depending on speed grade

Speed grade T requires the VDD_CORE voltage to be 0.85V if using
the maximum core frequency.

Speed grades G, K, S allow the VDD_CORE voltage to be 0.75V up to the
maximum core frequency but allow to run at 0.85V.

For efficiency in manufacturing and code maintenance we use 0.85V for
the PMIC defaults and device tree settings and dynamically adjust the
voltage in the PMIC and device tree to 0.75V for lower speed SKU to
gain more than 100mW power consumption reduction.

Upstream-Status: Submitted [https://lore.kernel.org/all/20240117101743.3955852-1-max.oss.09@gmail.com/T/#t]

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index 3d699f3205..5897d5d792 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -13,10 +13,13 @@
 #include <fdt_support.h>
 #include <init.h>
 #include <k3-ddrss.h>
+#include <power/regulator.h>
 #include <spl.h>
 
 #include "../common/tdx-cfg-block.h"
 
+#define VDD_CORE_REG "buck1"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -47,9 +50,37 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+static u32 get_vdd_core_nominal(void)
+{
+	int core_uvolt;
+
+	switch (k3_get_speed_grade()) {
+	case 'G':
+	case 'K':
+	case 'S':
+		core_uvolt = 750000;
+		break;
+	case 'T':
+	default:
+		core_uvolt = 850000;
+		break;
+	}
+	return core_uvolt;
+}
+
 #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+	int core_uvolt;
+
+	core_uvolt = get_vdd_core_nominal();
+	if (core_uvolt != 850000) {
+		do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1",
+				     "regulator-max-microvolt", core_uvolt, 0);
+		do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1",
+				     "regulator-min-microvolt", core_uvolt, 0);
+	}
+
 	return ft_common_board_setup(blob, bd);
 }
 #endif
@@ -84,6 +115,22 @@ static void select_dt_from_module_version(void)
 
 int board_late_init(void)
 {
+	int ret;
+	int core_uvolt;
+	struct udevice *dev = NULL;
+
+	core_uvolt = get_vdd_core_nominal();
+	if (core_uvolt != 850000) {
+		/* Set CPU core voltage to 0.75V for slower speed grades */
+		ret = regulator_get_by_devname(VDD_CORE_REG, &dev);
+		if (ret)
+			pr_err("VDD CORE Regulator get error: %d\n", ret);
+
+		ret = regulator_set_value_force(dev, core_uvolt);
+		if (ret)
+			pr_err("VDD CORE Regulator value setting error: %d\n", ret);
+	}
+
 	select_dt_from_module_version();
 
 	return 0;