board: ti: am57xx: Add board specific structures for ext_phy_regs

Beagle x15 phy_ctrl_const_regs structure is the common structure
for all AM57x platforms. Add board specific structure for
phy_ctrl_const_regs.

Update the emif_get_reg_dump() function to select phy_ctrl_const_regs
structure based on board name.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>

1 files changed, 309 insertions, 4 deletions

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 9ea507a8e9..7d7a88509a 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -194,6 +194,162 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 	0x0
 };
 
+static const u32 AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs[] = {
+	0x04040100,     /* EMIF1_EXT_PHY_CTRL_1  */
+	0x006B00C0,     /* EMIF1_EXT_PHY_CTRL_2  */
+	0x006B00BC,     /* EMIF1_EXT_PHY_CTRL_3  */
+	0x006B00C7,     /* EMIF1_EXT_PHY_CTRL_4  */
+	0x006B00C3,     /* EMIF1_EXT_PHY_CTRL_5  */
+	0x006B00D1,     /* EMIF1_EXT_PHY_CTRL_6  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_7  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_8  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_9  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_10 */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_11 */
+	0x00600071,     /* EMIF1_EXT_PHY_CTRL_12 */
+	0x00600075,     /* EMIF1_EXT_PHY_CTRL_13 */
+	0x0060007E,     /* EMIF1_EXT_PHY_CTRL_14 */
+	0x00600082,     /* EMIF1_EXT_PHY_CTRL_15 */
+	0x00600086,     /* EMIF1_EXT_PHY_CTRL_16 */
+	0x00400051,     /* EMIF1_EXT_PHY_CTRL_17 */
+	0x00400055,     /* EMIF1_EXT_PHY_CTRL_18 */
+	0x0040005E,     /* EMIF1_EXT_PHY_CTRL_19 */
+	0x00400062,     /* EMIF1_EXT_PHY_CTRL_20 */
+	0x00400066,     /* EMIF1_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF1_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF1_EXT_PHY_CTRL_25 */
+	0x000000B0,     /* EMIF1_EXT_PHY_CTRL_26 */
+	0x000000AC,     /* EMIF1_EXT_PHY_CTRL_27 */
+	0x000000B7,     /* EMIF1_EXT_PHY_CTRL_28 */
+	0x000000B3,     /* EMIF1_EXT_PHY_CTRL_29 */
+	0x000000C1,     /* EMIF1_EXT_PHY_CTRL_30 */
+	0x00000041,     /* EMIF1_EXT_PHY_CTRL_31 */
+	0x00000045,     /* EMIF1_EXT_PHY_CTRL_32 */
+	0x0000004E,     /* EMIF1_EXT_PHY_CTRL_33 */
+	0x00000052,     /* EMIF1_EXT_PHY_CTRL_34 */
+	0x00000056,     /* EMIF1_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF1_EXT_PHY_CTRL_36 */
+};
+
+static const u32 AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs[] = {
+	0x04040100,     /* EMIF1_EXT_PHY_CTRL_1  */
+	0x006B0081,     /* EMIF1_EXT_PHY_CTRL_2  */
+	0x006B0080,     /* EMIF1_EXT_PHY_CTRL_3  */
+	0x006B0086,     /* EMIF1_EXT_PHY_CTRL_4  */
+	0x006B0084,     /* EMIF1_EXT_PHY_CTRL_5  */
+	0x006B006B,     /* EMIF1_EXT_PHY_CTRL_6  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_7  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_8  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_9  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_10 */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_11 */
+	0x00600065,     /* EMIF1_EXT_PHY_CTRL_12 */
+	0x00600066,     /* EMIF1_EXT_PHY_CTRL_13 */
+	0x0060006A,     /* EMIF1_EXT_PHY_CTRL_14 */
+	0x0060006C,     /* EMIF1_EXT_PHY_CTRL_15 */
+	0x00600060,     /* EMIF1_EXT_PHY_CTRL_16 */
+	0x00400045,     /* EMIF1_EXT_PHY_CTRL_17 */
+	0x00400046,     /* EMIF1_EXT_PHY_CTRL_18 */
+	0x0040004A,     /* EMIF1_EXT_PHY_CTRL_19 */
+	0x0040004C,     /* EMIF1_EXT_PHY_CTRL_20 */
+	0x00400040,     /* EMIF1_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF1_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF1_EXT_PHY_CTRL_25 */
+	0x00000071,     /* EMIF1_EXT_PHY_CTRL_26 */
+	0x00000070,     /* EMIF1_EXT_PHY_CTRL_27 */
+	0x00000076,     /* EMIF1_EXT_PHY_CTRL_28 */
+	0x00000074,     /* EMIF1_EXT_PHY_CTRL_29 */
+	0x00000000,     /* EMIF1_EXT_PHY_CTRL_30 */
+	0x00000035,     /* EMIF1_EXT_PHY_CTRL_31 */
+	0x00000036,     /* EMIF1_EXT_PHY_CTRL_32 */
+	0x0000003A,     /* EMIF1_EXT_PHY_CTRL_33 */
+	0x0000003C,     /* EMIF1_EXT_PHY_CTRL_34 */
+	0x00000000,     /* EMIF1_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF1_EXT_PHY_CTRL_36 */
+};
+
+static const u32 AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs[] = {
+	0x04040100,     /* EMIF1_EXT_PHY_CTRL_1  */
+	0x006B00AF,     /* EMIF1_EXT_PHY_CTRL_2  */
+	0x006B00AB,     /* EMIF1_EXT_PHY_CTRL_3  */
+	0x006B00B4,     /* EMIF1_EXT_PHY_CTRL_4  */
+	0x006B00B1,     /* EMIF1_EXT_PHY_CTRL_5  */
+	0x006B00BD,     /* EMIF1_EXT_PHY_CTRL_6  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_7  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_8  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_9  */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_10 */
+	0x00320032,     /* EMIF1_EXT_PHY_CTRL_11 */
+	0x0060006E,     /* EMIF1_EXT_PHY_CTRL_12 */
+	0x00600071,     /* EMIF1_EXT_PHY_CTRL_13 */
+	0x00600078,     /* EMIF1_EXT_PHY_CTRL_14 */
+	0x0060007B,     /* EMIF1_EXT_PHY_CTRL_15 */
+	0x0060007F,     /* EMIF1_EXT_PHY_CTRL_16 */
+	0x0040004E,     /* EMIF1_EXT_PHY_CTRL_17 */
+	0x00400051,     /* EMIF1_EXT_PHY_CTRL_18 */
+	0x00400058,     /* EMIF1_EXT_PHY_CTRL_19 */
+	0x0040005B,     /* EMIF1_EXT_PHY_CTRL_20 */
+	0x0040005F,     /* EMIF1_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF1_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF1_EXT_PHY_CTRL_25 */
+	0x0000009F,     /* EMIF1_EXT_PHY_CTRL_26 */
+	0x0000009B,     /* EMIF1_EXT_PHY_CTRL_27 */
+	0x000000A4,     /* EMIF1_EXT_PHY_CTRL_28 */
+	0x000000A1,     /* EMIF1_EXT_PHY_CTRL_29 */
+	0x000000AD,     /* EMIF1_EXT_PHY_CTRL_30 */
+	0x0000003E,     /* EMIF1_EXT_PHY_CTRL_31 */
+	0x00000041,     /* EMIF1_EXT_PHY_CTRL_32 */
+	0x00000048,     /* EMIF1_EXT_PHY_CTRL_33 */
+	0x0000004B,     /* EMIF1_EXT_PHY_CTRL_34 */
+	0x0000004F,     /* EMIF1_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF1_EXT_PHY_CTRL_36 */
+};
+
+static const u32 AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs[] = {
+	0x04040100,     /* EMIF1_EXT_PHY_CTRL_1  */
+	0x006B00C0,     /* EMIF1_EXT_PHY_CTRL_2  */
+	0x006B00BC,     /* EMIF1_EXT_PHY_CTRL_3  */
+	0x006B00C7,     /* EMIF1_EXT_PHY_CTRL_4  */
+	0x006B00C3,     /* EMIF1_EXT_PHY_CTRL_5  */
+	0x006B00D1,     /* EMIF1_EXT_PHY_CTRL_6  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_7  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_8  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_9  */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_10 */
+	0x002F002F,     /* EMIF1_EXT_PHY_CTRL_11 */
+	0x00600071,     /* EMIF1_EXT_PHY_CTRL_12 */
+	0x00600075,     /* EMIF1_EXT_PHY_CTRL_13 */
+	0x0060007E,     /* EMIF1_EXT_PHY_CTRL_14 */
+	0x00600082,     /* EMIF1_EXT_PHY_CTRL_15 */
+	0x00600086,     /* EMIF1_EXT_PHY_CTRL_16 */
+	0x00400051,     /* EMIF1_EXT_PHY_CTRL_17 */
+	0x00400055,     /* EMIF1_EXT_PHY_CTRL_18 */
+	0x0040005E,     /* EMIF1_EXT_PHY_CTRL_19 */
+	0x00400062,     /* EMIF1_EXT_PHY_CTRL_20 */
+	0x00400066,     /* EMIF1_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF1_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF1_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF1_EXT_PHY_CTRL_25 */
+	0x000000B0,     /* EMIF1_EXT_PHY_CTRL_26 */
+	0x000000AC,     /* EMIF1_EXT_PHY_CTRL_27 */
+	0x000000B7,     /* EMIF1_EXT_PHY_CTRL_28 */
+	0x000000B3,     /* EMIF1_EXT_PHY_CTRL_29 */
+	0x000000C1,     /* EMIF1_EXT_PHY_CTRL_30 */
+	0x00000041,     /* EMIF1_EXT_PHY_CTRL_31 */
+	0x00000045,     /* EMIF1_EXT_PHY_CTRL_32 */
+	0x0000004E,     /* EMIF1_EXT_PHY_CTRL_33 */
+	0x00000052,     /* EMIF1_EXT_PHY_CTRL_34 */
+	0x00000056,     /* EMIF1_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF1_EXT_PHY_CTRL_36 */
+};
+
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config_init		= 0x61851b32,
 	.sdram_config			= 0x61851b32,
@@ -257,6 +413,123 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 	0x0
 };
 
+static const u32 AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs[] = {
+	0x04040100,     /* EMIF2_EXT_PHY_CTRL_1  */
+	0x006B0084,     /* EMIF2_EXT_PHY_CTRL_2  */
+	0x006B0087,     /* EMIF2_EXT_PHY_CTRL_3  */
+	0x006B007F,     /* EMIF2_EXT_PHY_CTRL_4  */
+	0x006B0080,     /* EMIF2_EXT_PHY_CTRL_5  */
+	0x006B006B,     /* EMIF2_EXT_PHY_CTRL_6  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_7  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_8  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_9  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_10 */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_11 */
+	0x0060006A,     /* EMIF2_EXT_PHY_CTRL_12 */
+	0x00600067,     /* EMIF2_EXT_PHY_CTRL_13 */
+	0x00600065,     /* EMIF2_EXT_PHY_CTRL_14 */
+	0x00600064,     /* EMIF2_EXT_PHY_CTRL_15 */
+	0x00600060,     /* EMIF2_EXT_PHY_CTRL_16 */
+	0x0040004A,     /* EMIF2_EXT_PHY_CTRL_17 */
+	0x00400047,     /* EMIF2_EXT_PHY_CTRL_18 */
+	0x00400045,     /* EMIF2_EXT_PHY_CTRL_19 */
+	0x00400044,     /* EMIF2_EXT_PHY_CTRL_20 */
+	0x00400040,     /* EMIF2_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF2_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF2_EXT_PHY_CTRL_25 */
+	0x00000074,     /* EMIF2_EXT_PHY_CTRL_26 */
+	0x00000077,     /* EMIF2_EXT_PHY_CTRL_27 */
+	0x0000006F,     /* EMIF2_EXT_PHY_CTRL_28 */
+	0x00000070,     /* EMIF2_EXT_PHY_CTRL_29 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_30 */
+	0x0000003A,     /* EMIF2_EXT_PHY_CTRL_31 */
+	0x00000037,     /* EMIF2_EXT_PHY_CTRL_32 */
+	0x00000035,     /* EMIF2_EXT_PHY_CTRL_33 */
+	0x00000034,     /* EMIF2_EXT_PHY_CTRL_34 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF2_EXT_PHY_CTRL_36 */
+};
+
+static const u32 AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs[] = {
+	0x04040100,     /* EMIF2_EXT_PHY_CTRL_1  */
+	0x006B00AB,     /* EMIF2_EXT_PHY_CTRL_2  */
+	0x006B00AB,     /* EMIF2_EXT_PHY_CTRL_3  */
+	0x006B00B4,     /* EMIF2_EXT_PHY_CTRL_4  */
+	0x006B00B2,     /* EMIF2_EXT_PHY_CTRL_5  */
+	0x006B006B,     /* EMIF2_EXT_PHY_CTRL_6  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_7  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_8  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_9  */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_10 */
+	0x00320032,     /* EMIF2_EXT_PHY_CTRL_11 */
+	0x00600073,     /* EMIF2_EXT_PHY_CTRL_12 */
+	0x00600074,     /* EMIF2_EXT_PHY_CTRL_13 */
+	0x00600078,     /* EMIF2_EXT_PHY_CTRL_14 */
+	0x0060007A,     /* EMIF2_EXT_PHY_CTRL_15 */
+	0x00600060,     /* EMIF2_EXT_PHY_CTRL_16 */
+	0x00400053,     /* EMIF2_EXT_PHY_CTRL_17 */
+	0x00400054,     /* EMIF2_EXT_PHY_CTRL_18 */
+	0x00400058,     /* EMIF2_EXT_PHY_CTRL_19 */
+	0x0040005A,     /* EMIF2_EXT_PHY_CTRL_20 */
+	0x00400040,     /* EMIF2_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF2_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF2_EXT_PHY_CTRL_25 */
+	0x0000009B,     /* EMIF2_EXT_PHY_CTRL_26 */
+	0x0000009B,     /* EMIF2_EXT_PHY_CTRL_27 */
+	0x000000A4,     /* EMIF2_EXT_PHY_CTRL_28 */
+	0x000000A2,     /* EMIF2_EXT_PHY_CTRL_29 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_30 */
+	0x00000043,     /* EMIF2_EXT_PHY_CTRL_31 */
+	0x00000044,     /* EMIF2_EXT_PHY_CTRL_32 */
+	0x00000048,     /* EMIF2_EXT_PHY_CTRL_33 */
+	0x0000004A,     /* EMIF2_EXT_PHY_CTRL_34 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF2_EXT_PHY_CTRL_36 */
+};
+
+static const u32 AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs[] = {
+	0x04040100,     /* EMIF2_EXT_PHY_CTRL_1  */
+	0x006B00BC,     /* EMIF2_EXT_PHY_CTRL_2  */
+	0x006B00BB,     /* EMIF2_EXT_PHY_CTRL_3  */
+	0x006B00C7,     /* EMIF2_EXT_PHY_CTRL_4  */
+	0x006B00C4,     /* EMIF2_EXT_PHY_CTRL_5  */
+	0x006B006B,     /* EMIF2_EXT_PHY_CTRL_6  */
+	0x002F002F,     /* EMIF2_EXT_PHY_CTRL_7  */
+	0x002F002F,     /* EMIF2_EXT_PHY_CTRL_8  */
+	0x002F002F,     /* EMIF2_EXT_PHY_CTRL_9  */
+	0x002F002F,     /* EMIF2_EXT_PHY_CTRL_10 */
+	0x002F002F,     /* EMIF2_EXT_PHY_CTRL_11 */
+	0x00600078,     /* EMIF2_EXT_PHY_CTRL_12 */
+	0x00600079,     /* EMIF2_EXT_PHY_CTRL_13 */
+	0x0060007E,     /* EMIF2_EXT_PHY_CTRL_14 */
+	0x00600081,     /* EMIF2_EXT_PHY_CTRL_15 */
+	0x00600060,     /* EMIF2_EXT_PHY_CTRL_16 */
+	0x00400058,     /* EMIF2_EXT_PHY_CTRL_17 */
+	0x00400059,     /* EMIF2_EXT_PHY_CTRL_18 */
+	0x0040005E,     /* EMIF2_EXT_PHY_CTRL_19 */
+	0x00400061,     /* EMIF2_EXT_PHY_CTRL_20 */
+	0x00400040,     /* EMIF2_EXT_PHY_CTRL_21 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_22 */
+	0x00800080,     /* EMIF2_EXT_PHY_CTRL_23 */
+	0x40010080,     /* EMIF2_EXT_PHY_CTRL_24 */
+	0x08102040,     /* EMIF2_EXT_PHY_CTRL_25 */
+	0x000000AC,     /* EMIF2_EXT_PHY_CTRL_26 */
+	0x000000AB,     /* EMIF2_EXT_PHY_CTRL_27 */
+	0x000000B7,     /* EMIF2_EXT_PHY_CTRL_28 */
+	0x000000B4,     /* EMIF2_EXT_PHY_CTRL_29 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_30 */
+	0x00000048,     /* EMIF2_EXT_PHY_CTRL_31 */
+	0x00000049,     /* EMIF2_EXT_PHY_CTRL_32 */
+	0x0000004E,     /* EMIF2_EXT_PHY_CTRL_33 */
+	0x00000051,     /* EMIF2_EXT_PHY_CTRL_34 */
+	0x00000000,     /* EMIF2_EXT_PHY_CTRL_35 */
+	0x00000077      /* EMIF2_EXT_PHY_CTRL_36 */
+};
+
 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 	.sdram_config_init		= 0x61863332,
 	.sdram_config			= 0x61863332,
@@ -334,12 +607,44 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 {
 	switch (emif_nr) {
 	case 1:
-		*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
-		*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+		if (board_is_am572x_evm()) {
+			*regs = AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs);
+		} else if (board_is_am574x_idk()) {
+			*regs = AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs);
+		} else if (board_is_am572x_idk()) {
+			*regs = AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs);
+		} else if (board_is_am571x_idk()) {
+			*regs = AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs);
+		} else {
+			*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+			*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+		}
 		break;
 	case 2:
-		*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
-		*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+		if (board_is_am572x_evm()) {
+			*regs = AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs);
+		} else if (board_is_am574x_idk()) {
+			*regs = AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs);
+		} else if (board_is_am572x_idk()) {
+			*regs = AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs;
+			*size = ARRAY_SIZE
+				(AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs);
+		} else {
+			*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+			*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+		}
 		break;
 	}
 }