Merge branch 'next'

Merge all outstanding changes from the current next branch in now that
we have released.

156 files changed, 1301 insertions, 14331 deletions

diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
index 1a62bbf12e..cd3c33e407 100644
--- a/board/boundary/nitrogen6x/6x_upgrade.txt
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -1,4 +1,4 @@
-setenv stdout serial,vga
+setenv stdout serial,vidconsole
 echo "check U-Boot" ;
 setenv offset 0x400
 if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 044cefd979..392a3f8f1d 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -627,6 +627,11 @@ int board_video_skip(void)
 	return 0;
 }
 
+int ipu_displays_init(void)
+{
+	return board_video_skip();
+}
+
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index adb56c6c87..84603cb117 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -368,8 +368,20 @@ U_BOOT_DEVICE(omapl138_uart) = {
 	.platdata = &serial_pdata,
 };
 
+static const struct davinci_mmc_plat mmc_platdata = {
+	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.cfg = {
+		.f_min = 200000,
+		.f_max = 25000000,
+		.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+		.host_caps = MMC_MODE_4BIT,
+		.b_max = DAVINCI_MAX_BLOCKS,
+		.name = "da830-mmc",
+	},
+};
 U_BOOT_DEVICE(omapl138_mmc) = {
 	.name = "davinci_mmc",
+	.platdata = &mmc_platdata,
 };
 
 void spl_board_init(void)
diff --git a/board/ea/mx7ulp_com/imximage.cfg b/board/ea/mx7ulp_com/imximage.cfg
index d298d17c1e..1b218996ae 100644
--- a/board/ea/mx7ulp_com/imximage.cfg
+++ b/board/ea/mx7ulp_com/imximage.cfg
@@ -28,7 +28,7 @@ BOOT_FROM	sd
 PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
 #else
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 /*
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
deleted file mode 100644
index 9bb667ab4f..0000000000
--- a/board/freescale/b4860qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_B4860QDS || TARGET_B4420QDS
-
-config SYS_BOARD
-	default "b4860qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "B4860QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
deleted file mode 100644
index 34ac099e44..0000000000
--- a/board/freescale/b4860qds/MAINTAINERS
+++ /dev/null
@@ -1,17 +0,0 @@
-B4860QDS BOARD
-M:	Ashish Kumar <ashish.kumar@nxp.com>
-S:	Maintained
-F:	board/freescale/b4860qds/
-F:	include/configs/B4860QDS.h
-F:	configs/B4420QDS_defconfig
-F:	configs/B4420QDS_NAND_defconfig
-F:	configs/B4420QDS_SPIFLASH_defconfig
-F:	configs/B4860QDS_defconfig
-F:	configs/B4860QDS_NAND_defconfig
-F:	configs/B4860QDS_SPIFLASH_defconfig
-F:	configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
-
-B4860QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/B4860QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
deleted file mode 100644
index c0ba2c0168..0000000000
--- a/board/freescale/b4860qds/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-else
-obj-y	+= b4860qds.o
-obj-$(CONFIG_TARGET_B4860QDS)	+= eth_b4860qds.o
-obj-$(CONFIG_TARGET_B4420QDS)	+= eth_b4860qds.o
-obj-$(CONFIG_PCI)	+= pci.o
-endif
-
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
deleted file mode 100644
index cc8ff11ba4..0000000000
--- a/board/freescale/b4860qds/b4860qds.c
+++ /dev/null
@@ -1,1276 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/idt8t49n222a_serdes_clk.h"
-#include "../common/zm7300.h"
-#include "b4860qds.h"
-#include "b4860qds_qixis.h"
-#include "b4860qds_crossbar_con.h"
-
-#define CLK_MUX_SEL_MASK	0x4
-#define ETH_PHY_CLK_OUT		0x4
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *const freq[] = {"100", "125", "156.25", "161.13",
-						"122.88", "122.88", "122.88"};
-	int clock;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-		QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw >= 0x8 && sw <= 0xE)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-		(int)QIXIS_READ(scver), qixis_read_tag(buf),
-		(int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference Clocks: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = (sw >> 5) & 7;
-	printf("Bank1=%sMHz ", freq[clock]);
-	sw = QIXIS_READ(brdcfg[4]);
-	clock = (sw >> 6) & 3;
-	printf("Bank2=%sMHz\n", freq[clock]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca(u8 ch)
-{
-	int ret;
-
-	/* Selecting proper channel via PCA*/
-	ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
-	if (ret) {
-		printf("PCA: failed to select proper channel.\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
-#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
-
-static inline int read_voltage(void)
-{
-	int i, ret, voltage_read = 0;
-	u16 vol_mon;
-
-	for (i = 0; i < NUM_READINGS; i++) {
-		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
-			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-		if (ret) {
-			printf("VID: failed to read core voltage\n");
-			return ret;
-		}
-		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
-			printf("VID: Core voltage sensor error\n");
-			return -1;
-		}
-		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
-		/* LSB = 4mv */
-		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
-		udelay(WAIT_FOR_ADC);
-	}
-	/* calculate the average */
-	voltage_read /= NUM_READINGS;
-
-	return voltage_read;
-}
-
-static int adjust_vdd(ulong vdd_override)
-{
-	int re_enable = disable_interrupts();
-	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 fusesr;
-	u8 vid;
-	int vdd_target, vdd_last;
-	int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
-	int ret;
-	unsigned int orig_i2c_speed;
-	unsigned long vdd_string_override;
-	char *vdd_string;
-	static const uint16_t vdd[32] = {
-		0,	/* unused */
-		9875,	/* 0.9875V */
-		9750,
-		9625,
-		9500,
-		9375,
-		9250,
-		9125,
-		9000,
-		8875,
-		8750,
-		8625,
-		8500,
-		8375,
-		8250,
-		8125,
-		10000,	/* 1.0000V */
-		10125,
-		10250,
-		10375,
-		10500,
-		10625,
-		10750,
-		10875,
-		11000,
-		0,	/* reserved */
-	};
-	struct vdd_drive {
-		u8 vid;
-		unsigned voltage;
-	};
-
-	ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
-	if (ret) {
-		printf("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* get the voltage ID from fuse status register */
-	fusesr = in_be32(&gur->dcfg_fusesr);
-	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
-		FSL_CORENET_DCFG_FUSESR_VID_MASK;
-	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
-		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
-			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
-	}
-	vdd_target = vdd[vid];
-	debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
-	      vid, vdd_target/10);
-
-	/* check override variable for overriding VDD */
-	vdd_string = env_get("b4qds_vdd_mv");
-	if (vdd_override == 0 && vdd_string &&
-	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
-		vdd_override = vdd_string_override;
-	if (vdd_override >= 819 && vdd_override <= 1212) {
-		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
-		debug("VDD override is %lu\n", vdd_override);
-	} else if (vdd_override != 0) {
-		printf("Invalid value.\n");
-	}
-
-	if (vdd_target == 0) {
-		printf("VID: VID not used\n");
-		ret = 0;
-		goto exit;
-	}
-
-	/*
-	 * Read voltage monitor to check real voltage.
-	 * Voltage monitor LSB is 4mv.
-	 */
-	vdd_last = read_voltage();
-	if (vdd_last < 0) {
-		printf("VID: abort VID adjustment\n");
-		ret = -1;
-		goto exit;
-	}
-
-	debug("VID: Core voltage is at %d mV\n", vdd_last);
-	ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
-	if (ret) {
-		printf("VID: I2c failed to switch channel to DPM\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* Round up to the value of step of Voltage regulator */
-	voltage = roundup(vdd_target, ZM_STEP);
-	debug("VID: rounded up voltage = %d\n", voltage);
-
-	/* lower the speed to 100kHz to access ZM7300 device */
-	debug("VID: Setting bus speed to 100KHz if not already set\n");
-	orig_i2c_speed = i2c_get_bus_speed();
-	if (orig_i2c_speed != 100000)
-		i2c_set_bus_speed(100000);
-
-	/* Read the existing level on board, if equal to requsted one,
-	   no need to re-set */
-	existing_voltage = zm_read_voltage();
-
-	/* allowing the voltage difference of one step 0.0125V acceptable */
-	if ((existing_voltage >= voltage) &&
-	    (existing_voltage < (voltage + ZM_STEP))) {
-		debug("VID: voltage already set as requested,returning\n");
-		ret = existing_voltage;
-		goto out;
-	}
-	debug("VID: Changing voltage for board from %dmV to %dmV\n",
-	      existing_voltage/10, voltage/10);
-
-	if (zm_disable_wp() < 0) {
-		ret = -1;
-		goto out;
-	}
-	/* Change Voltage: the change is done through all the steps in the
-	   way, to avoid reset to the board due to power good signal fail
-	   in big voltage change gap jump.
-	*/
-	if (existing_voltage > voltage) {
-		temp_voltage = existing_voltage - ZM_STEP;
-			while (temp_voltage >= voltage) {
-				ret = zm_write_voltage(temp_voltage);
-				if (ret == temp_voltage) {
-					temp_voltage -= ZM_STEP;
-				} else {
-					/* ZM7300 device failed to set
-					 * the voltage */
-					printf
-					("VID:Stepping down vol failed:%dmV\n",
-					 temp_voltage/10);
-				     ret = -1;
-				     goto out;
-				}
-			}
-	} else {
-		temp_voltage = existing_voltage + ZM_STEP;
-			while (temp_voltage < (voltage + ZM_STEP)) {
-				ret = zm_write_voltage(temp_voltage);
-				if (ret == temp_voltage) {
-					temp_voltage += ZM_STEP;
-				} else {
-					/* ZM7300 device failed to set
-					 * the voltage */
-					printf
-					("VID:Stepping up vol failed:%dmV\n",
-					 temp_voltage/10);
-				     ret = -1;
-				     goto out;
-				}
-			}
-	}
-
-	if (zm_enable_wp() < 0)
-		ret = -1;
-
-	/* restore the speed to 400kHz */
-out:	debug("VID: Restore the I2C bus speed to %dKHz\n",
-				orig_i2c_speed/1000);
-	i2c_set_bus_speed(orig_i2c_speed);
-	if (ret < 0)
-		goto exit;
-
-	ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
-	if (ret) {
-		printf("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-	vdd_last = read_voltage();
-	select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-	if (vdd_last > 0)
-		printf("VID: Core voltage %d mV\n", vdd_last);
-	else
-		ret = -1;
-
-exit:
-	if (re_enable)
-		enable_interrupts();
-	return ret;
-}
-
-int configure_vsc3316_3308(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	unsigned int num_vsc16_con, num_vsc08_con;
-	u32 serdes1_prtcl, serdes2_prtcl;
-	int ret;
-	char buffer[HWCONFIG_BUFFER_SIZE];
-	char *buf = NULL;
-
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return 0;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		printf("SERDES2 is not enabled\n");
-		return 0;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2a:
-	case 0x2C:
-	case 0x2D:
-	case 0x2E:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B: SGMII
-			 * Lanes: C,D,E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar to use onboard SGMII PHYs:"
-				"srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_4sfp_sgmii_12_56,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_4sfp_sgmii_12_56,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-
-	case 0x01:
-	case 0x02:
-	case 0x04:
-	case 0x05:
-	case 0x06:
-	case 0x07:
-	case 0x08:
-	case 0x09:
-	case 0x0A:
-	case 0x0B:
-	case 0x0C:
-	case 0x2F:
-	case 0x30:
-	case 0x32:
-	case 0x33:
-	case 0x34:
-	case 0x39:
-	case 0x3A:
-	case 0x3C:
-	case 0x3D:
-	case 0x5C:
-	case 0x5D:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B: AURORA
-			 * Lanes: C,d: SGMII
-			 * Lanes: E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
-				" and CPRI. srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sfp_sgmii_aurora,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sfp_sgmii_aurora,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-
-#ifdef CONFIG_ARCH_B4420
-	case 0x17:
-	case 0x18:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B,C,D: SGMII
-			 * Lanes: E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar to use onboard SGMII PHYs:"
-				"srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sgmii_lane_cd, num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sgmii_lane_cd, num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-#endif
-
-	case 0x3E:
-	case 0x0D:
-	case 0x0E:
-	case 0x12:
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sfp, num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sfp, num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-	default:
-		printf("WARNING:VSC crossbars programming not supported for:%x"
-					" SerDes1 Protocol.\n", serdes1_prtcl);
-		return -1;
-	}
-
-	num_vsc08_con = NUM_CON_VSC3308;
-	/* Configure VSC3308 crossbar switch */
-	ret = select_i2c_ch_pca(I2C_CH_VSC3308);
-	switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
-	case 0x9d:
-#endif
-	case 0x9E:
-	case 0x9A:
-	case 0x98:
-	case 0x48:
-	case 0x49:
-	case 0x4E:
-	case 0x79:
-	case 0x7A:
-		if (!ret) {
-			ret = vsc3308_config(VSC3308_TX_ADDRESS,
-					vsc08_tx_amc, num_vsc08_con);
-			if (ret)
-				return ret;
-			ret = vsc3308_config(VSC3308_RX_ADDRESS,
-					vsc08_rx_amc, num_vsc08_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-	case 0x80:
-	case 0x81:
-	case 0x82:
-	case 0x83:
-	case 0x84:
-	case 0x85:
-	case 0x86:
-	case 0x87:
-	case 0x88:
-	case 0x89:
-	case 0x8a:
-	case 0x8b:
-	case 0x8c:
-	case 0x8d:
-	case 0x8e:
-	case 0xb1:
-	case 0xb2:
-		if (!ret) {
-			/*
-			 * Extract hwconfig from environment since environment
-			 * is not setup properly yet
-			 */
-			env_get_f("hwconfig", buffer, sizeof(buffer));
-			buf = buffer;
-
-			if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
-						  "sfp_amc", "sfp", buf)) {
-#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
-				/* change default VSC3308 for XFI erratum */
-				ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
-						vsc08_tx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
-						vsc08_rx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-#else
-				ret = vsc3308_config(VSC3308_TX_ADDRESS,
-						vsc08_tx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config(VSC3308_RX_ADDRESS,
-						vsc08_rx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-#endif
-			} else {
-				ret = vsc3308_config(VSC3308_TX_ADDRESS,
-						vsc08_tx_amc, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config(VSC3308_RX_ADDRESS,
-						vsc08_rx_amc, num_vsc08_con);
-				if (ret)
-					return ret;
-			}
-
-		} else {
-			return ret;
-		}
-		break;
-	default:
-		printf("WARNING:VSC crossbars programming not supported for: %x"
-					" SerDes2 Protocol.\n", serdes2_prtcl);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
-{
-	u32 rst_err;
-
-	/* Steps For SerDes PLLs reset and reconfiguration
-	 * or PLL power-up procedure
-	 */
-	debug("CALIBRATE PLL:%d\n", pll_num);
-	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-			SRDS_RSTCTL_SDRST_B);
-	udelay(10);
-	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-	udelay(10);
-	setbits_be32(&srds_regs->bank[pll_num].rstctl,
-			SRDS_RSTCTL_RST);
-	setbits_be32(&srds_regs->bank[pll_num].rstctl,
-		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-		| SRDS_RSTCTL_SDRST_B));
-
-	udelay(20);
-
-	/* Check whether PLL has been locked or not */
-	rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
-				SRDS_RSTCTL_RSTERR;
-	rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
-	debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
-	if (rst_err)
-		return rst_err;
-
-	return rst_err;
-}
-
-static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
-{
-	int ret = 0;
-	u32 fcap, dcbias, bcap, pllcr1, pllcr0;
-
-	if (calibrate_pll(srds_regs, pll_num)) {
-		/* STEP 1 */
-		/* Read fcap, dcbias and bcap value */
-		clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-				SRDS_PLLCR0_DCBIAS_OUT_EN);
-		fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_FCAP;
-		fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
-		bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_BCAP_EN;
-		bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
-		setbits_be32(&srds_regs->bank[pll_num].pllcr0,
-				SRDS_PLLCR0_DCBIAS_OUT_EN);
-		dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_DCBIAS;
-		dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-		debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
-					bcap, fcap, dcbias);
-		if (fcap == 0 && bcap == 1) {
-			/* Step 3 */
-			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_EN);
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_OVD);
-			if (calibrate_pll(srds_regs, pll_num)) {
-				/*save the fcap, dcbias and bcap values*/
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OUT_EN);
-				fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
-					& SRDS_PLLSR2_FCAP;
-				fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
-				bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
-					& SRDS_PLLSR2_BCAP_EN;
-				bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
-				setbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OUT_EN);
-				dcbias = in_be32
-					(&srds_regs->bank[pll_num].pllsr2) &
-							SRDS_PLLSR2_DCBIAS;
-				dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-
-				/* Step 4*/
-				clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BYP_CAL);
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BCAP_EN);
-				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BCAP_OVD);
-				/* change the fcap and dcbias to the saved
-				 * values from Step 3 */
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-							SRDS_PLLCR1_PLL_FCAP);
-				pllcr1 = (in_be32
-					(&srds_regs->bank[pll_num].pllcr1)|
-					(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
-				out_be32(&srds_regs->bank[pll_num].pllcr1,
-							pllcr1);
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OVRD);
-				pllcr0 = (in_be32
-				(&srds_regs->bank[pll_num].pllcr0)|
-				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
-				out_be32(&srds_regs->bank[pll_num].pllcr0,
-							pllcr0);
-				ret = calibrate_pll(srds_regs, pll_num);
-				if (ret)
-					return ret;
-			} else {
-				goto out;
-			}
-		} else { /* Step 5 */
-			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-			udelay(10);
-			/* Change the fcap, dcbias, and bcap to the
-			 * values from Step 1 */
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BYP_CAL);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_PLL_FCAP);
-			pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
-				(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
-			out_be32(&srds_regs->bank[pll_num].pllcr1,
-						pllcr1);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OVRD);
-			pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
-				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
-			out_be32(&srds_regs->bank[pll_num].pllcr0,
-						pllcr0);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_EN);
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_OVD);
-			ret = calibrate_pll(srds_regs, pll_num);
-			if (ret)
-				return ret;
-		}
-	}
-out:
-	return 0;
-}
-
-static int check_serdes_pll_locks(void)
-{
-	serdes_corenet_t *srds1_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	serdes_corenet_t *srds2_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
-	int i, ret1, ret2;
-
-	debug("\nSerDes1 Lock check\n");
-	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-		ret1 = check_pll_locks(srds1_regs, i);
-		if (ret1) {
-			printf("SerDes1, PLL:%d didnt lock\n", i);
-			return ret1;
-		}
-	}
-	debug("\nSerDes2 Lock check\n");
-	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-		ret2 = check_pll_locks(srds2_regs, i);
-		if (ret2) {
-			printf("SerDes2, PLL:%d didnt lock\n", i);
-			return ret2;
-		}
-	}
-
-	return 0;
-}
-
-int config_serdes1_refclks(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 serdes1_prtcl, lane;
-	unsigned int flag_sgmii_aurora_prtcl = 0;
-	int i;
-	int ret = 0;
-
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return -1;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	/* To prevent generation of reset request from SerDes
-	 * while changing the refclks, By setting SRDS_RST_MSK bit,
-	 * SerDes reset event cannot cause a reset request
-	 */
-	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
-	/* Reconfigure IDT idt8t49n222a device for CPRI to work
-	 * For this SerDes1's Refclk1 and refclk2 need to be set
-	 * to 122.88MHz
-	 */
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2A:
-	case 0x2C:
-	case 0x2D:
-	case 0x2E:
-	case 0x01:
-	case 0x02:
-	case 0x04:
-	case 0x05:
-	case 0x06:
-	case 0x07:
-	case 0x08:
-	case 0x09:
-	case 0x0A:
-	case 0x0B:
-	case 0x0C:
-	case 0x2F:
-	case 0x30:
-	case 0x32:
-	case 0x33:
-	case 0x34:
-	case 0x39:
-	case 0x3A:
-	case 0x3C:
-	case 0x3D:
-	case 0x5C:
-	case 0x5D:
-		debug("Configuring idt8t49n222a for CPRI SerDes clks:"
-			" for srds_prctl:%x\n", serdes1_prtcl);
-		ret = select_i2c_ch_pca(I2C_CH_IDT);
-		if (!ret) {
-			ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
-					SERDES_REFCLK_122_88,
-					SERDES_REFCLK_122_88, 0);
-			if (ret) {
-				printf("IDT8T49N222A configuration failed.\n");
-				goto out;
-			} else
-				debug("IDT8T49N222A configured.\n");
-		} else {
-			goto out;
-		}
-		select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-		/* Change SerDes1's Refclk1 to 125MHz for on board
-		 * SGMIIs or Aurora to work
-		 */
-		for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
-			enum srds_prtcl lane_prtcl = serdes_get_prtcl
-						(0, serdes1_prtcl, lane);
-			switch (lane_prtcl) {
-			case SGMII_FM1_DTSEC1:
-			case SGMII_FM1_DTSEC2:
-			case SGMII_FM1_DTSEC3:
-			case SGMII_FM1_DTSEC4:
-			case SGMII_FM1_DTSEC5:
-			case SGMII_FM1_DTSEC6:
-			case AURORA:
-				flag_sgmii_aurora_prtcl++;
-				break;
-			default:
-				break;
-			}
-		}
-
-		if (flag_sgmii_aurora_prtcl)
-			QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-
-		/* Steps For SerDes PLLs reset and reconfiguration after
-		 * changing SerDes's refclks
-		 */
-		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-			debug("For PLL%d reset and reconfiguration after"
-			       " changing refclks\n", i+1);
-			clrbits_be32(&srds_regs->bank[i].rstctl,
-					SRDS_RSTCTL_SDRST_B);
-			udelay(10);
-			clrbits_be32(&srds_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-			udelay(10);
-			setbits_be32(&srds_regs->bank[i].rstctl,
-					SRDS_RSTCTL_RST);
-			setbits_be32(&srds_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				| SRDS_RSTCTL_SDRST_B));
-		}
-		break;
-	default:
-		printf("WARNING:IDT8T49N222A configuration not"
-			" supported for:%x SerDes1 Protocol.\n",
-			serdes1_prtcl);
-	}
-
-out:
-	/* Clearing SRDS_RST_MSK bit as now
-	 * SerDes reset event can cause a reset request
-	 */
-	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-	return ret;
-}
-
-int config_serdes2_refclks(void)
-{
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_corenet_t *srds2_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
-	u32 serdes2_prtcl;
-	int ret = 0;
-	int i;
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		debug("SERDES2 is not enabled\n");
-		return -ENODEV;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	/* To prevent generation of reset request from SerDes
-	 * while changing the refclks, By setting SRDS_RST_MSK bit,
-	 * SerDes reset event cannot cause a reset request
-	 */
-	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
-	/* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
-	 * For this SerDes2's Refclk1 need to be set to 100MHz
-	 */
-	switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
-	case 0x9d:
-#endif
-	case 0x9E:
-	case 0x9A:
-		/* fallthrough */
-	case 0xb1:
-	case 0xb2:
-		debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
-			serdes2_prtcl);
-		ret = select_i2c_ch_pca(I2C_CH_IDT);
-		if (!ret) {
-			ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
-					SERDES_REFCLK_100,
-					SERDES_REFCLK_156_25, 0);
-			if (ret) {
-				printf("IDT8T49N222A configuration failed.\n");
-				goto out;
-			} else
-				debug("IDT8T49N222A configured.\n");
-		} else {
-			goto out;
-		}
-		select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-		/* Steps For SerDes PLLs reset and reconfiguration after
-		 * changing SerDes's refclks
-		 */
-		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-			clrbits_be32(&srds2_regs->bank[i].rstctl,
-					SRDS_RSTCTL_SDRST_B);
-			udelay(10);
-			clrbits_be32(&srds2_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-			udelay(10);
-			setbits_be32(&srds2_regs->bank[i].rstctl,
-					SRDS_RSTCTL_RST);
-			setbits_be32(&srds2_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				| SRDS_RSTCTL_SDRST_B));
-
-			udelay(10);
-		}
-		break;
-	default:
-		printf("IDT configuration not supported for:%x S2 Protocol.\n",
-			serdes2_prtcl);
-	}
-
-out:
-	/* Clearing SRDS_RST_MSK bit as now
-	 * SerDes reset event can cause a reset request
-	 */
-	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-	return ret;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-	int ret;
-	u32 svr = SVR_SOC_VER(get_svr());
-
-	/* Create law for MAPLE only for personalities having MAPLE */
-	if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
-	    (svr == SVR_B4420) || (svr == SVR_B4220)) {
-		set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
-			     LAW_TRGT_IF_MAPLE);
-	}
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	/*
-	 * Adjust core voltage according to voltage ID
-	 * This function changes I2C mux to channel 2.
-	 */
-	if (adjust_vdd(0) < 0)
-		printf("Warning: Adjusting core voltage failed\n");
-
-	/* SerDes1 refclks need to be set again, as default clks
-	 * are not suitable for CPRI and onboard SGMIIs to work
-	 * simultaneously.
-	 * This function will set SerDes1's Refclk1 and refclk2
-	 * as per SerDes1 protocols
-	 */
-	if (config_serdes1_refclks())
-		printf("SerDes1 Refclks couldn't set properly.\n");
-	else
-		printf("SerDes1 Refclks have been set.\n");
-
-	/* SerDes2 refclks need to be set again, as default clks
-	 * are not suitable for PCIe SATA to work
-	 * This function will set SerDes2's Refclk1 and refclk2
-	 * for SerDes2 protocols having PCIe in them
-	 * for PCIe SATA to work
-	 */
-	ret = config_serdes2_refclks();
-	if (!ret)
-		printf("SerDes2 Refclks have been set.\n");
-	else if (ret == -ENODEV)
-		printf("SerDes disable, Refclks couldn't change.\n");
-	else
-		printf("SerDes2 Refclk reconfiguring failed.\n");
-
-#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
-			defined(CONFIG_SYS_FSL_ERRATUM_A006475)
-	/* Rechecking the SerDes locks after all SerDes configurations
-	 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
-	 * and at cold temperatures.
-	 * Following sequence ensure the proper locking of SerDes PLLs.
-	 */
-	if (SVR_MAJ(get_svr()) == 1) {
-		if (check_serdes_pll_locks())
-			printf("SerDes plls still not locked properly.\n");
-		else
-			printf("SerDes plls have been locked well.\n");
-	}
-#endif
-
-	/* Configure VSC3316 and VSC3308 crossbar switches */
-	if (configure_vsc3316_3308())
-		printf("VSC:failed to configure VSC3316/3308.\n");
-	else
-		printf("VSC:VSC3316/3308 successfully configured.\n");
-
-	select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((sysclk_conf & 0x0C) >> 2) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (ddrclk_conf & 0x03) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-static int serdes_refclock(u8 sw, u8 sdclk)
-{
-	unsigned int clock;
-	int ret = -1;
-	u8 brdcfg4;
-
-	if (sdclk == 1) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
-			return SRDS_PLLCR0_RFCK_SEL_125;
-		else
-			clock = (sw >> 5) & 7;
-	} else
-		clock = (sw >> 6) & 3;
-
-	switch (clock) {
-	case 0:
-		ret = SRDS_PLLCR0_RFCK_SEL_100;
-		break;
-	case 1:
-		ret = SRDS_PLLCR0_RFCK_SEL_125;
-		break;
-	case 2:
-		ret = SRDS_PLLCR0_RFCK_SEL_156_25;
-		break;
-	case 3:
-		ret = SRDS_PLLCR0_RFCK_SEL_161_13;
-		break;
-	case 4:
-	case 5:
-	case 6:
-		ret = SRDS_PLLCR0_RFCK_SEL_122_88;
-		break;
-	default:
-		ret = -1;
-		break;
-	}
-
-	return ret;
-}
-
-#define NUM_SRDS_BANKS	2
-
-int misc_init_r(void)
-{
-	u8 sw;
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 actual[NUM_SRDS_BANKS];
-	unsigned int i;
-	int clock;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = serdes_refclock(sw, 1);
-	if (clock >= 0)
-		actual[0] = clock;
-	else
-		printf("Warning: SDREFCLK1 switch setting is unsupported\n");
-
-	sw = QIXIS_READ(brdcfg[4]);
-	clock = serdes_refclock(sw, 2);
-	if (clock >= 0)
-		actual[1] = clock;
-	else
-		printf("Warning: SDREFCLK2 switch setting unsupported\n");
-
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 pllcr0 = srds_regs->bank[i].pllcr0;
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("Warning: SERDES bank %u expects reference clock"
-			       " %sMHz, but actual is %sMHz\n", i + 1,
-			       serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
-
-/*
- * Dump board switch settings.
- * The bits that cannot be read/sampled via some FPGA or some
- * registers, they will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
-	int i;
-	u8 sw[5];
-
-	/*
-	 * Any bit with 1 means that bit cannot be reverse engineered.
-	 * It will be displayed as _ in binary format.
-	 */
-	static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
-	char buf[10];
-	u8 brdcfg[16], dutcfg[16];
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	sw[0] = ((brdcfg[0] & 0x0f) << 4)	| \
-		(brdcfg[9] & 0x08);
-	sw[1] = ((dutcfg[1] & 0x01) << 7)	| \
-		((dutcfg[2] & 0x07) << 4)       | \
-		((dutcfg[6] & 0x10) >> 1)       | \
-		((dutcfg[6] & 0x80) >> 5)       | \
-		((dutcfg[1] & 0x40) >> 5)       | \
-		(dutcfg[6] & 0x01);
-	sw[2] = dutcfg[0];
-	sw[3] = 0;
-	sw[4] = ((brdcfg[1] & 0x30) << 2)	| \
-		((brdcfg[1] & 0xc0) >> 2)	| \
-		(brdcfg[1] & 0x0f);
-
-	puts("DIP switch settings:\n");
-	for (i = 0; i < 5; i++) {
-		printf("SW%d         = 0b%s (0x%02x)\n",
-			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
-	}
-}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
deleted file mode 100644
index 4a8e91b58f..0000000000
--- a/board/freescale/b4860qds/b4860qds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
deleted file mode 100644
index b9d59c23be..0000000000
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CROSSBAR_CONNECTIONS_H__
-#define __CROSSBAR_CONNECTIONS_H__
-
-#define NUM_CON_VSC3316	8
-#define NUM_CON_VSC3308	4
-
-static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
-				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
-
-static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
-				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {2, 14}, {12, 15},
-				{-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {5, 14}, {4, 15},
-				{-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {5, 14},
-				{4, 15}, {2, 12}, {12, 13} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
-			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
-				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
-
-static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
-				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 3}, {15, 12},
-				{-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 11}, {15, 10},
-				{-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 11},
-				{15, 10}, {13, 3}, {12, 12} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
-			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
-
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
-
-static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
-
-static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
deleted file mode 100644
index d4299d8af1..0000000000
--- a/board/freescale/b4860qds/b4860qds_qixis.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __B4860QDS_QIXIS_H__
-#define __B4860QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for B4860QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* CLK */
-#define QIXIS_CLK_66		0x0
-#define QIXIS_CLK_100		0x1
-#define QIXIS_CLK_125		0x2
-#define QIXIS_CLK_133		0x3
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-
-/* SGMII */
-#define PHY_BASE_ADDR		0x18
-#define PORT_NUM		0x04
-#define REGNUM			0x00
-#endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
deleted file mode 100644
index 05377bac5b..0000000000
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
deleted file mode 100644
index 597d3914ca..0000000000
--- a/board/freescale/b4860qds/b4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x2A_0x98
-140e0018 0f001218 00000000 00000000
-54980000 9000a000 e8104000 a9000000
-01000000 00000000 00000000 0001b1f8
-00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
deleted file mode 100644
index d3aa349ddf..0000000000
--- a/board/freescale/b4860qds/ddr.c
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <fsl_ddr.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 2,
-	.rank_density = 2147483648u,
-	.capacity = 4294967296u,
-	.primary_sdram_width = 64,
-	.ec_sdram_width = 8,
-	.registered_dimm = 0,
-	.mirrored_dimm = 1,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 2,	/* ECC */
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1071,
-	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
-	.taa_ps = 13910,
-	.twr_ps = 15000,
-	.trcd_ps = 13910,
-	.trrd_ps = 6000,
-	.trp_ps = 13910,
-	.tras_ps = 34000,
-	.trc_ps = 48910,
-	.trfc_ps = 260000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 35000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "RAW timing DDR";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
-	{2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
-	{2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
-	{1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
-	{1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
-	{1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x3e;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	puts("Initializing....using SPD\n");
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size =  fsl_ddr_sdram_size();
-#endif
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
-			  unsigned int dbw_cap_adj[])
-{
-	int i, j;
-	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
-	unsigned long long rank_density, ctlr_density = 0;
-
-	current_mem_base = 0ull;
-	total_mem = 0;
-	/*
-	 * This board has soldered DDR chips. DDRC1 has two rank.
-	 * DDRC2 has only one rank.
-	 * Assigning DDRC2 to lower address and DDRC1 to higher address.
-	 */
-	if (pinfo->memctl_opts[0].memctl_interleaving) {
-		rank_density = pinfo->dimm_params[0][0].rank_density >>
-					dbw_cap_adj[0];
-		ctlr_density = rank_density;
-
-		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
-		      rank_density, ctlr_density);
-		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
-			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
-			case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			case FSL_DDR_PAGE_INTERLEAVING:
-			case FSL_DDR_BANK_INTERLEAVING:
-			case FSL_DDR_SUPERBANK_INTERLEAVING:
-				total_ctlr_mem = 2 * ctlr_density;
-				break;
-			default:
-				panic("Unknown interleaving mode");
-			}
-			pinfo->common_timing_params[i].base_address =
-						current_mem_base;
-			pinfo->common_timing_params[i].total_mem =
-						total_ctlr_mem;
-			total_mem = current_mem_base + total_ctlr_mem;
-			debug("ctrl %d base 0x%llx\n", i, current_mem_base);
-			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-		}
-	} else {
-		/*
-		 * Simple linear assignment if memory
-		 * controllers are not interleaved.
-		 */
-		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
-			total_ctlr_mem = 0;
-			pinfo->common_timing_params[i].base_address =
-						current_mem_base;
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				/* Compute DIMM base addresses. */
-				unsigned long long cap =
-					pinfo->dimm_params[i][j].capacity;
-				pinfo->dimm_params[i][j].base_address =
-					current_mem_base;
-				debug("ctrl %d dimm %d base 0x%llx\n",
-				      i, j, current_mem_base);
-				current_mem_base += cap;
-				total_ctlr_mem += cap;
-			}
-			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-			pinfo->common_timing_params[i].total_mem =
-							total_ctlr_mem;
-			total_mem += total_ctlr_mem;
-		}
-	}
-	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
-
-	return total_mem;
-}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
deleted file mode 100644
index 6d5f3d1fda..0000000000
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Sandeep Kumar Singh <sandeep@freescale.com>
- */
-
-/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
- * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
- * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
- * one Fman device on B4860. The SERDES configuration is used to determine
- * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
- * to which PHYs. So for a given Fman MAC, there is one and only PHY it
- * connects to. MACs cannot be routed to PHYs dynamically. This configuration
- * is done at boot time by reading SERDES protocol from RCW.
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-#define EMI_NONE       0xFFFFFFFF
-
-#ifdef CONFIG_FMAN_ENET
-
-/*
- * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
- * lane at index is mapped to slot number n. A value of '0' will mean
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
-	0, 0, 0, 0,
-	0, 0, 0, 0,
-	1, 1, 1, 1,
-	0, 0, 0, 0
-};
-
-/*
- * This function initializes the lane_to_slot[] array. It reads RCW to check
- * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
- * lane_to_slot[] accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	unsigned int  serdes2_prtcl;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Initializing lane to slot: Serdes2 protocol: %x\n",
-			serdes2_prtcl);
-
-	switch (serdes2_prtcl) {
-	case 0x17:
-	case 0x18:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: SGMII
-		 * Lanes: E,F: Aur
-		 * Lanes: G,H: SRIO
-		 */
-	case 0x91:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: SGMII
-		 * Lanes: C,D: SRIO2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x93:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: SGMII
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x98:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: XAUI2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x9a:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: PCI
-		 * Lanes: C,D: SGMII
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x9e:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: PCI
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0xb1:
-	case 0xb2:
-	case 0x8c:
-	case 0x8d:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: PCI
-		 * Lanes: E,F: SGMII 3&4
-		 * Lanes: G,H: XFI
-		 */
-	case 0xc2:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: SGMII
-		 * Lanes: C,D: SRIO2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-		lane_to_slot[12] = 2;
-		lane_to_slot[13] = lane_to_slot[12];
-		lane_to_slot[14] = lane_to_slot[12];
-		lane_to_slot[15] = lane_to_slot[12];
-		break;
-
-	default:
-		printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
-				serdes2_prtcl);
-			break;
-	}
-	return;
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	struct memac_mdio_info tg_memac_mdio_info;
-	unsigned int i;
-	unsigned int  serdes1_prtcl, serdes2_prtcl;
-	int qsgmii;
-	struct mii_dev *bus;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return 0;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		printf("SERDES2 is not enabled\n");
-		return 0;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	printf("Initializing Fman\n");
-
-	initialize_lane_to_slot();
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	tg_memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the real 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tg_memac_mdio_info);
-
-	/*
-	 * Program the two on board DTSEC PHY addresses assuming that they are
-	 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
-	 * 6 to on board SGMII phys
-	 */
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2a:
-		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
-		debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
-		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
-		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC5,
-				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6,
-				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		break;
-#ifdef CONFIG_ARCH_B4420
-	case 0x17:
-	case 0x18:
-		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
-		debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
-		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
-		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		/* Fixing Serdes clock by programming FPGA register */
-		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		break;
-#endif
-	default:
-		printf("Fman:  Unsupported SerDes1 Protocol 0x%02x\n",
-				serdes1_prtcl);
-		break;
-	}
-	switch (serdes2_prtcl) {
-	case 0x17:
-	case 0x18:
-		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
-		break;
-	case 0x48:
-	case 0x49:
-		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
-		break;
-	case 0xb1:
-	case 0xb2:
-	case 0x8c:
-	case 0x8d:
-		debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		/*
-		 * XFI does not need a PHY to work, but to make U-Boot
-		 * happy, assign a fake PHY address for a XFI port.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 0);
-		fm_info_set_phy_address(FM1_10GEC2, 1);
-		break;
-	case 0x98:
-		/* XAUI in Slot1 and Slot2 */
-		debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
-		      CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC1,
-					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-		debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
-		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2,
-					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		break;
-	case 0x9E:
-		/* XAUI in Slot2 */
-		debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
-		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2,
-					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		break;
-	default:
-		printf("Fman:  Unsupported SerDes2 Protocol 0x%02x\n",
-				serdes2_prtcl);
-		break;
-	}
-
-	/*set PHY address for QSGMII Riser Card on slot2*/
-	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
-
-	if (qsgmii) {
-		switch (serdes2_prtcl) {
-		case 0xb2:
-		case 0x8d:
-			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
-			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			fm_info_set_mdio(i,
-				miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-			break;
-		case PHY_INTERFACE_MODE_NONE:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: DTSEC%u set to unknown interface %i\n",
-					idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		int idx = i - FM1_10GEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			fm_info_set_mdio(i,
-					 miiphy_get_dev_by_name
-					 (DEFAULT_FM_TGEC_MDIO_NAME));
-			break;
-		case PHY_INTERFACE_MODE_NONE:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: TGEC%u set to unknown interface %i\n",
-			       idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	int phy;
-	char alias[32];
-	struct fixed_link f_link;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
-	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		phy = fm_info_get_phy_address(port);
-
-		sprintf(alias, "phy_sgmii_%x", phy);
-		fdt_set_phy_handle(fdt, compat, addr, alias);
-		fdt_status_okay_by_alias(fdt, alias);
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		/* check if it's XFI interface for 10g */
-		switch (prtcl2) {
-		case 0x80:
-		case 0x81:
-		case 0x82:
-		case 0x83:
-		case 0x84:
-		case 0x85:
-		case 0x86:
-		case 0x87:
-		case 0x88:
-		case 0x89:
-		case 0x8a:
-		case 0x8b:
-		case 0x8c:
-		case 0x8d:
-		case 0x8e:
-		case 0xb1:
-		case 0xb2:
-			f_link.phy_id = port;
-			f_link.duplex = 1;
-			f_link.link_speed = 10000;
-			f_link.pause = 0;
-			f_link.asym_pause = 0;
-
-			fdt_delprop(fdt, offset, "phy-handle");
-			fdt_setprop(fdt, offset, "fixed-link", &f_link,
-				    sizeof(f_link));
-			break;
-		case 0x98: /* XAUI interface */
-			strcpy(alias, "phy_xaui_slot1");
-			fdt_status_okay_by_alias(fdt, alias);
-
-			strcpy(alias, "phy_xaui_slot2");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		case 0x9e: /* XAUI interface */
-		case 0x9a:
-		case 0x93:
-		case 0x91:
-			strcpy(alias, "phy_xaui_slot1");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		case 0x97: /* XAUI interface */
-		case 0xc3:
-			strcpy(alias, "phy_xaui_slot2");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-/*
- * Set status to disabled for unused ethernet node
- */
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i;
-	char alias[32];
-
-	for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_NONE:
-			sprintf(alias, "ethernet%u", i);
-			fdt_status_disabled_by_alias(fdt, alias);
-			break;
-		default:
-			break;
-		}
-	}
-}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
deleted file mode 100644
index b39d720068..0000000000
--- a/board/freescale/b4860qds/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
deleted file mode 100644
index 45dd461e77..0000000000
--- a/board/freescale/b4860qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
deleted file mode 100644
index fe5ce35013..0000000000
--- a/board/freescale/b4860qds/spl.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((sysclk_conf & 0x0C) >> 2) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (ddrclk_conf & 0x03) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, uart_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("" : : : "memory");
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	uart_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     uart_clk / 16 / CONFIG_BAUDRATE);
-
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
-	env_init();
-	env_relocate();
-#else
-	/* relocate environment function pointers etc. */
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-#endif
-
-	i2c_init_all();
-
-	puts("\n\n");
-
-	dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
deleted file mode 100644
index 68e2295cb5..0000000000
--- a/board/freescale/b4860qds/tlb.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
-	 * space is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 11, BOOKE_PAGESZ_64K, 1),
-#endif
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_4K, 1),
-
-	/*
-	 * *I*G - SRIO
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for SRIO2.
-	 */
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
-	/* *I*G* - SRIO1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
-	/* *I*G* - SRIO2 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 16, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
-	 * fetching ucode and ENV from master
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 17, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 17, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig
deleted file mode 100644
index dd9f765d7d..0000000000
--- a/board/freescale/bsc9131rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_BSC9131RDB
-
-config SYS_BOARD
-	default "bsc9131rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "BSC9131RDB"
-
-endif
diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS
deleted file mode 100644
index 272d4ad3aa..0000000000
--- a/board/freescale/bsc9131rdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-BSC9131RDB BOARD
-M:	Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S:	Maintained
-F:	board/freescale/bsc9131rdb/
-F:	include/configs/BSC9131RDB.h
-F:	configs/BSC9131RDB_NAND_defconfig
-F:	configs/BSC9131RDB_NAND_SYSCLK100_defconfig
-F:	configs/BSC9131RDB_SPIFLASH_defconfig
-F:	configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
deleted file mode 100644
index 063db4495e..0000000000
--- a/board/freescale/bsc9131rdb/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011-2012 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-obj-y	+= bsc9131rdb.o
-obj-y	+= ddr.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
deleted file mode 100644
index c8405970c1..0000000000
--- a/board/freescale/bsc9131rdb/README
+++ /dev/null
@@ -1,151 +0,0 @@
-Overview
---------
-- BSC9131 is integrated device that targets Femto base station market.
- It combines Power Architecture e500v2 and DSP StarCore SC3850 core
- technologies with MAPLE-B2F baseband acceleration processing elements.
-- It's MAPLE disabled personality is called 9231.
-
-The BSC9131 SoC includes the following function and features:
-. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
-  L2 cache
-. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
-. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
-  Processing (MAPLE-B2F)
-. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
- Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
- and CRC algorithms
-. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
- Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
- operations
-. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
- ECC, up to 400-MHz clock/800 MHz data rate
-. Dedicated security engine featuring trusted boot
-. DMA controller
-. OCNDMA with four bidirectional channels
-. Interfaces
-. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
-  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
-. eTSEC 1 supports RGMII/RMII
-. eTSEC 2 supports RGMII
-. High-speed USB 2.0 host and device controller with ULPI interface
-. Enhanced secure digital (SD/MMC) host controller (eSDHC)
-. Antenna interface controller (AIC), supporting three industry standard
-  JESD207/three custom ADI RF interfaces (two dual port and one single port)
-  and three MAXIM's MaxPHY serial interfaces
-. ADI lanes support both full duplex FDD support and half duplex TDD support
-. Universal Subscriber Identity Module (USIM) interface that facilitates
-  communication to SIM cards or Eurochip pre-paid phone cards
-. TDM with one TDM port
-. Two DUART, four eSPI, and two I2C controllers
-. Integrated Flash memory controller (IFC)
-. TDM with 256 channels
-. GPIO
-. Sixteen 32-bit timers
-
-The e500 core subsystem within the Power Architecture consists of the following:
-. 32-Kbyte L1 instruction cache
-. 32-Kbyte L1 data cache
-. 256-Kbyte L2 cache/L2 memory/L2 stash
-. programmable interrupt controller (PIC)
-. Debug support
-. Timers
-
-The SC3850 core subsystem consists of the following:
-. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
-. 32 Kbyte 8-way level 1 data cache (L1 DCache)
-. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
-. Memory management unit (MMU)
-. Enhanced programmable interrupt controller (EPIC)
-. Debug and profiling unit (DPU)
-. Two 32-bit timers
-
-BSC9131RDB board Overview
--------------------------
- 1Gbyte DDR3 (on board DDR)
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- USB-ULPI
- eTSEC1: Connected to RGMII PHY
- eTSEC2: Connected to RGMII PHY
- DUART interface: supports one UARTs up to 115200 bps for console display
- USIM connector
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. 1000/500/800
-2. 800/400/667
-
-Boot Methods Supported
------------------------
-1. NAND Flash
-2. SPI Flash
-
-Default Boot Method
---------------------
-NAND boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9131RDB:
-1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
-	make BSC9131RDB_NAND
-2. NAND Flash with sysclk 100MHz(J16 on RDB open)
-	make BSC9131RDB_NAND_SYSCLK100
-3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
-	make BSC9131RDB_SPIFLASH
-4. SPI Flash with sysclk 100MHz(J16 on RDB open)
-	make BSC9131RDB_SPIFLASH_SYSCLK100
-
-Memory map
------------
- 0x0000_0000	0x7FFF_FFFF	DDR			1G cacheable
- 0xA0000000	0xBFFFFFFF	Shared DSP core L2/M2 space	512M
- 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
- 0xC1F0_0000	0xC1F3_FFFF	PA SRAM Region 0	256K
- 0xC1F8_0000	0xC1F9_FFFF	PA SRAM Region 1	128K
- 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
- 0xFEE0_0000	0xFEE0_0FFF	DSP Boot ROM		4K
- 0xFF60_0000	0xFF6F_FFFF 	DSP CCSR		1M
- 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
- 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M
-
-DDR Memory map
----------------
- 0x0000_0000	0x36FF_FFFF	Memory passed onto Linux
- 0x3700_0000	0x37FF_FFFF	PowerPC-DSP shared control area
- 0x3800_0000	0x4FFF_FFFF	DSP Private area
-
- Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
- data communcation between PowerPC and DSP core.
- Rest is PowerPC private area.
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
-	tftp 1000000 u-boot-nand.bin
-	nand erase 0 100000
-	nand write 1000000 0 100000
-	reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-	dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
-
-Likely, that .dts file will come from here;
-
-	linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
-	tftp 1000000 uImage
-	tftp 2000000 rootfs.ext2.gz.uboot
-	tftp c00000 bsc9131rdb.dtb
-	bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
deleted file mode 100644
index 75c2aec75d..0000000000
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-#include <netdev.h>
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
-
-	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
-			MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
-	setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
-	clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
-			MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
-			MPC85xx_PMUXCR_IFC_AD_GPIO |
-			MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	struct cpu_type *cpu;
-
-	cpu = gd->arch.cpu;
-	printf("Board: %sRDB\n", cpu->name);
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
-	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
deleted file mode 100644
index 0951d7758a..0000000000
--- a/board/freescale/bsc9131rdb/ddr.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE	1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
-	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{750, 850, &ddr_cfg_regs_800},
-	{0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
-	int i;
-	char buf[32];
-	fsl_ddr_cfg_regs_t ddr_cfg_regs;
-	phys_size_t ddr_size;
-	ulong ddr_freq, ddr_freq_mhz;
-
-	ddr_freq = get_ddr_freq(0);
-	ddr_freq_mhz = ddr_freq / 1000000;
-
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
-
-	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
-		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
-		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
-			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
-							sizeof(ddr_cfg_regs));
-			break;
-		}
-	}
-
-	if (fixed_ddr_parm_0[i].max_freq == 0) {
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
-	}
-
-	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
-					LAW_TRGT_IF_DDR_1) < 0) {
-		printf("ERROR setting Local Access Windows for DDR\n");
-		return 0;
-	}
-
-	return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J256M8HX-15E */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 1073741824u,
-	.capacity = 1073741824u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1870,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 15000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
deleted file mode 100644
index ccfe4a2410..0000000000
--- a/board/freescale/bsc9131rdb/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
-		LAW_TRGT_IF_DSP_CCSR),
-	SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
-		LAW_TRGT_IF_OCN_DSP),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
deleted file mode 100644
index 4ae9ba06c8..0000000000
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* Initialize the DDR3 */
-	sdram_init();
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
deleted file mode 100644
index e1aacf0607..0000000000
--- a/board/freescale/bsc9131rdb/tlb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
-	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR (PA) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* CCSRBAR (DSP) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
-		      CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-			0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 3, BOOKE_PAGESZ_1M, 1)
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig
deleted file mode 100644
index e5499e6129..0000000000
--- a/board/freescale/bsc9132qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_BSC9132QDS
-
-config SYS_BOARD
-	default "bsc9132qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "BSC9132QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS
deleted file mode 100644
index 95abe3d408..0000000000
--- a/board/freescale/bsc9132qds/MAINTAINERS
+++ /dev/null
@@ -1,25 +0,0 @@
-BSC9132QDS BOARD
-M:	Naveen Burmi <naveen.burmi@nxp.com>
-S:	Maintained
-F:	board/freescale/bsc9132qds/
-F:	include/configs/BSC9132QDS.h
-F:	configs/BSC9132QDS_NAND_DDRCLK100_defconfig
-F:	configs/BSC9132QDS_NAND_DDRCLK133_defconfig
-F:	configs/BSC9132QDS_NOR_DDRCLK100_defconfig
-F:	configs/BSC9132QDS_NOR_DDRCLK133_defconfig
-F:	configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
-F:	configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
-F:	configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
-F:	configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
-
-BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
-F:	configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
-F:	configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
-F:	configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
-F:	configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
-F:	configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
-F:	configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
-F:	configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
deleted file mode 100644
index dcbdf42147..0000000000
--- a/board/freescale/bsc9132qds/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-obj-y	+= bsc9132qds.o
-obj-y	+= ddr.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
deleted file mode 100644
index ede95d41da..0000000000
--- a/board/freescale/bsc9132qds/README
+++ /dev/null
@@ -1,150 +0,0 @@
-Overview
---------
- The BSC9132 is a highly integrated device that targets the evolving
- Microcell, Picocell, and Enterprise-Femto base station market subsegments.
-
- The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
- core technologies with MAPLE-B2P baseband acceleration processing elements
- to address the need for a high performance, low cost, integrated solution
- that handles all required processing layers without the need for an
- external device except for an RF transceiver or, in a Micro base station
- configuration, a host device that handles the L3/L4 and handover between
- sectors.
-
- The BSC9132 SoC includes the following function and features:
-    - Power Architecture subsystem including two e500 processors with
-	512-Kbyte shared L2 cache
-    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
-	cache
-    - 32 Kbyte of shared M3 memory
-    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
-      Processing (MAPLE-B2P)
-    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
-      ECC), up to 1333 MHz data rate
-    - Dedicated security engine featuring trusted boot
-    - Two DMA controllers
-	 - OCNDMA with four bidirectional channels
-	 - SysDMA with sixteen bidirectional channels
-    - Interfaces
-	- Four-lane SerDes PHY
-	    - PCI Express controller complies with the PEX Specification-Rev 2.0
-	- Two Common Public Radio Interface (CPRI) controller lanes
-	    - High-speed USB 2.0 host and device controller with ULPI interface
-	- Enhanced secure digital (SD/MMC) host controller (eSDHC)
-	    - Antenna interface controller (AIC), supporting four industry
-		standard JESD207/four custom ADI RF interfaces
-       - ADI lanes support both full duplex FDD support & half duplex TDD
-       - Universal Subscriber Identity Module (USIM) interface that
-	   facilitates communication to SIM cards or Eurochip pre-paid phone
-	   cards
-       - Two DUART, two eSPI, and two I2C controllers
-       - Integrated Flash memory controller (IFC)
-       - GPIO
-     - Sixteen 32-bit timers
-
-The SC3850 core subsystem consists of the following:
- - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
- - 32 KB, 8-way, level 1 data cache (L1 DCache)
- - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
- - Memory management unit (MMU)
- - Global interrupt controller ( GIC)
- - Debug and profiling unit (DPU)
- - Two 32-bit quad timers
-
-BSC9132QDS board Overview
--------------------------
- 2Gbyte DDR3 (on board DDR), Dual Ranki
- 32Mbyte 16bit NOR flash
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- SD slot
- USB-ULPI
- eTSEC1: Connected to SGMII PHY
- eTSEC2: Connected to SGMII PHY
- PCIe
- CPRI
- SerDes
- I2C RTC
- DUART interface: supports one UARTs up to 115200 bps for console display
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
-     (SYSCLK = 100MHz, DDRCLK = 100MHz)
-2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
-     (SYSCLK = 100MHz, DDRCLK = 133MHz)
-
-Boot Methods Supported
------------------------
-1. NOR Flash
-2. NAND Flash
-3. SD Card
-4. SPI flash
-
-Default Boot Method
---------------------
-NOR boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9132QDS:
-1. NOR Flash
-	make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
-	make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
-2. NAND Flash : It is currently not supported
-3. SPI Flash
-	make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
-	make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
-4. SD Card
-	make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
-	make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
-
-Memory map
------------
- 0x0000_0000	0x7FFF_FFFF	DDR			2G cacheable
- 0x8000_0000	0x8FFF_FFFF	NOR Flash		256M
- 0x9000_0000	0x9FFF_FFFF	PCIe Memory 		256M
- 0xA000_0000	0xA7FF_FFFF	DSP core1 L2 space	128M
- 0xB000_0000	0xB0FF_FFFF	DSP core0 M2 space	16M
- 0xB100_0000	0xB1FF_FFFF	DSP core1 M2 space	16M
- 0xC000_0000	0xC000_7FFF	M3 Memory		32K
- 0xC001_0000	0xC001_FFFF	PCI Express I/O		64K
- 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
- 0xC1F0_0000	0xC1F7_FFFF	PA SRAM Region 0	512K
- 0xC1F8_0000	0xC1FB_FFFF	PA SRAM Region 1	512K
- 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
- 0xFEE0_0000	0xFEE0_0FFF	DSP Boot ROM		4K
- 0xFF60_0000	0xFF6F_FFFF 	DSP CCSR		1M
- 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
- 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
-	tftp 1000000 u-boot-nand.bin
-	nand erase 0 100000
-	nand write 1000000 0 100000
-	reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-	dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
-
-Likely, that .dts file will come from here;
-
-	linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
-	tftp 1000000 uImage
-	tftp 2000000 rootfs.ext2.gz.uboot
-	tftp c00000 bsc9132qds.dtb
-	bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
deleted file mode 100644
index 6870674f7a..0000000000
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ /dev/null
@@ -1,432 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#endif
-
-#include "../common/qixis.h"
-DECLARE_GLOBAL_DATA_PTR;
-
-
-int board_early_init_f(void)
-{
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
-	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
-	return 0;
-}
-
-void board_config_serdes_mux(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-
-	switch (srds_cfg) {
-	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
-	case  1:
-	case  2:
-	case  3:
-	case  4:
-	case  5:
-	case 22:
-	case 23:
-	case 24:
-	case 25:
-	case 26:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
-		break;
-
-	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
-	case  6:
-	case  7:
-	case  8:
-	case  9:
-	case 10:
-	case 27:
-	case 28:
-	case 29:
-	case 30:
-	case 31:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
-		break;
-
-	/* PEX(1) PEX(2) SGMII1 SGMII2 */
-	case 11:
-	case 32:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
-		break;
-
-	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
-	case 12:
-	case 13:
-	case 14:
-	case 15:
-	case 16:
-	case 33:
-	case 34:
-	case 35:
-	case 36:
-	case 37:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
-		break;
-
-	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
-	case 17:
-	case 18:
-	case 19:
-	case 20:
-	case 21:
-	case 38:
-	case 39:
-	case 40:
-	case 41:
-	case 42:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
-		break;
-
-	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
-	case 43:
-	case 44:
-	case 45:
-	case 46:
-	case 47:
-		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
-		break;
-
-
-	default:
-		break;
-	}
-}
-
-/* Configure DSP DDR controller */
-void dsp_ddr_configure(void)
-{
-	/*
-	 *There are separate DDR-controllers for DSP and PowerPC side DDR.
-	 *copy the ddr controller settings from PowerPC side DDR controller
-	 *to the DSP DDR controller as connected DDR memories are similar.
-	 */
-	struct ccsr_ddr __iomem *pa_ddr =
-			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-	struct ccsr_ddr temp_ddr;
-	struct ccsr_ddr __iomem *dsp_ddr =
-			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
-
-	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
-	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
-	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
-	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
-	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
-	set_tlb(1, flashbase + 0x4000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
-#endif
-	board_config_serdes_mux();
-	dsp_ddr_configure();
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int checkboard(void)
-{
-	struct cpu_type *cpu;
-	u8 sw;
-
-	cpu = gd->arch.cpu;
-	printf("Board: %sQDS\n", cpu->name);
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
-	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	printf("IFC chip select:");
-	switch (sw) {
-	case 0:
-		printf("NOR\n");
-		break;
-	case 2:
-		printf("Promjet\n");
-		break;
-	case 4:
-		printf("NAND\n");
-		break;
-	default:
-		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-		break;
-	}
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-
-#endif
-
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-
-	#ifdef CONFIG_PCI
-	pci_eth_init(bis);
-	#endif
-
-	return 0;
-}
-
-#define USBMUX_SEL_MASK		0xc0
-#define USBMUX_SEL_UART2	0xc0
-#define USBMUX_SEL_USB		0x40
-#define SPIMUX_SEL_UART3	0x80
-#define GPS_MUX_SEL_GPS		0x40
-
-#define TSEC_1588_CLKIN_MASK	0x03
-#define CON_XCVR_REF_CLK	0x00
-
-int misc_init_r(void)
-{
-	u8 val;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 porbmsr = in_be32(&gur->porbmsr);
-	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
-	/*Configure 1588 clock-in source from RF Card*/
-	val = QIXIS_READ_I2C(brdcfg[5]);
-	QIXIS_WRITE_I2C(brdcfg[5],
-		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
-
-	if (hwconfig("uart2") && hwconfig("usb1")) {
-		printf("UART2 and USB cannot work together on the board\n");
-		printf("Remove one from hwconfig and reset\n");
-	} else {
-		if (hwconfig("uart2")) {
-			val = QIXIS_READ_I2C(brdcfg[5]);
-			QIXIS_WRITE_I2C(brdcfg[5],
-				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
-			clrbits_be32(&gur->pmuxcr3,
-						MPC85xx_PMUXCR3_USB_SEL_MASK);
-			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
-		} else {
-			/* By default USB should be selected.
-			* Programming FPGA to select USB. */
-			val = QIXIS_READ_I2C(brdcfg[5]);
-			QIXIS_WRITE_I2C(brdcfg[5],
-				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
-		}
-
-	}
-
-	if (hwconfig("sim")) {
-		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
-			romloc == PORBMSR_ROMLOC_NOR ||
-			romloc == PORBMSR_ROMLOC_SPI) {
-
-			val = QIXIS_READ_I2C(brdcfg[3]);
-			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
-			clrbits_be32(&gur->pmuxcr,
-				MPC85xx_PMUXCR0_SIM_SEL_MASK);
-			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
-		}
-	}
-
-	if (hwconfig("uart3")) {
-		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
-			romloc == PORBMSR_ROMLOC_NOR ||
-			romloc == PORBMSR_ROMLOC_SDHC) {
-
-			/* UART3 and SPI1 (Flashes) are muxed together */
-			val = QIXIS_READ_I2C(brdcfg[3]);
-			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
-			clrbits_be32(&gur->pmuxcr3,
-						MPC85xx_PMUXCR3_UART3_SEL_MASK);
-			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
-
-			/* MUX to select UART3 connection to J24 header
-			 * or to GPS */
-			val = QIXIS_READ_I2C(brdcfg[6]);
-			if (hwconfig("gps"))
-				QIXIS_WRITE_I2C(brdcfg[6],
-						(val | GPS_MUX_SEL_GPS));
-			else
-				QIXIS_WRITE_I2C(brdcfg[6],
-						(val & ~(GPS_MUX_SEL_GPS)));
-		}
-	}
-	return 0;
-}
-
-void fdt_del_node_compat(void *blob, const char *compatible)
-{
-	int err;
-	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
-	if (off < 0) {
-		printf("WARNING: could not find compatible node %s: %s.\n",
-			compatible, fdt_strerror(off));
-		return;
-	}
-	err = fdt_del_node(blob, off);
-	if (err < 0) {
-		printf("WARNING: could not remove %s: %s.\n",
-			compatible, fdt_strerror(err));
-	}
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
-	{ "cfi-flash",			MTD_DEV_TYPE_NOR,  },
-	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	#if defined(CONFIG_PCI)
-	FT_FSL_PCI_SETUP;
-	#endif
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 porbmsr = in_be32(&gur->porbmsr);
-	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-
-	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
-		/* If uart2 is there in hwconfig remove usb node from
-		 *  device tree */
-
-		if (hwconfig("uart2")) {
-			/* remove dts usb node */
-			fdt_del_node_compat(blob, "fsl-usb2-dr");
-		} else {
-			fsl_fdt_fixup_dr_usb(blob, bd);
-			fdt_del_node_and_alias(blob, "serial2");
-		}
-	}
-
-	if (hwconfig("uart3")) {
-		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
-			romloc == PORBMSR_ROMLOC_NOR ||
-			romloc == PORBMSR_ROMLOC_SDHC)
-			/* Delete SPI node from the device tree */
-				fdt_del_node_and_alias(blob, "spi1");
-	} else
-		fdt_del_node_and_alias(blob, "serial3");
-
-	if (hwconfig("sim")) {
-		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
-			romloc == PORBMSR_ROMLOC_NOR ||
-			romloc == PORBMSR_ROMLOC_SPI) {
-
-			/* remove dts sdhc node */
-			fdt_del_node_compat(blob, "fsl,esdhc");
-		} else if (romloc == PORBMSR_ROMLOC_SDHC) {
-
-			/* remove dts sim node */
-			fdt_del_node_compat(blob, "fsl,sim-v1.0");
-			printf("SIM & SDHC can't work together on the board");
-			printf("\nRemove sim from hwconfig and reset\n");
-		}
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
deleted file mode 100644
index f4effe5a2d..0000000000
--- a/board/freescale/bsc9132qds/ddr.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
-	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
-	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{750, 850, &ddr_cfg_regs_800},
-	{1060, 1333, &ddr_cfg_regs_1333},
-	{0, 0, NULL}
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
-	int i;
-	char buf[32];
-	fsl_ddr_cfg_regs_t ddr_cfg_regs;
-	phys_size_t ddr_size;
-	ulong ddr_freq, ddr_freq_mhz;
-
-	ddr_freq = get_ddr_freq(0);
-	ddr_freq_mhz = ddr_freq / 1000000;
-
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
-
-	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
-		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
-		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
-			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
-							sizeof(ddr_cfg_regs));
-			break;
-		}
-	}
-
-	if (fixed_ddr_parm_0[i].max_freq == 0)
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
-
-	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
-					LAW_TRGT_IF_DDR_1) < 0) {
-		printf("ERROR setting Local Access Windows for DDR\n");
-		return 0;
-	}
-
-	return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J512M8_187E */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 1073741824u,
-	.capacity = 1073741824u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1870,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 15000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
deleted file mode 100644
index 6dca3d1751..0000000000
--- a/board/freescale/bsc9132qds/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_FPGA_BASE_PHYS
-	SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
-	SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
-		LAW_TRGT_IF_DSP_CCSR),
-	SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
-		LAW_TRGT_IF_OCN_DSP),
-	SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
-		LAW_TRGT_IF_CLASS_DSP),
-	SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
-		LAW_TRGT_IF_CLASS_DSP)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
deleted file mode 100644
index dd56ad6b2b..0000000000
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_init(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-#if CONFIG_DDR_CLK_FREQ == 100000000
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#elif CONFIG_DDR_CLK_FREQ == 133000000
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-#else
-	puts("Not a valid DDR Freq Found! Please Reset\n");
-#endif
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* Initialize the DDR3 */
-	sdram_init();
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
deleted file mode 100644
index 9466814172..0000000000
--- a/board/freescale/bsc9132qds/tlb.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
-	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR (PA) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* CCSRBAR (DSP) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
-		      CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
-		      MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-			0, 3, BOOKE_PAGESZ_64M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
-			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-			0, 4, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 6, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 7, BOOKE_PAGESZ_64K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_FPGA_BASE
-		/* *I*G - Board FPGA  */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 9, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig
deleted file mode 100644
index 51e25c39df..0000000000
--- a/board/freescale/c29xpcie/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_C29XPCIE
-
-config SYS_BOARD
-	default "c29xpcie"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "C29XPCIE"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
deleted file mode 100644
index 44af12cdbe..0000000000
--- a/board/freescale/c29xpcie/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-C29XPCIE BOARD
-M:	Po Liu <po.liu@nxp.com>
-S:	Maintained
-F:	board/freescale/c29xpcie/
-F:	include/configs/C29XPCIE.h
-F:	configs/C29XPCIE_defconfig
-F:	configs/C29XPCIE_NAND_defconfig
-F:	configs/C29XPCIE_SPIFLASH_defconfig
-F:	configs/C29XPCIE_NOR_SECBOOT_defconfig
-F:	configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
deleted file mode 100644
index 2a9c1be802..0000000000
--- a/board/freescale/c29xpcie/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-MINIMAL=
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-endif
-obj-y	+= c29xpcie.o
-obj-y	+= cpld.o
-obj-y	+= ddr.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README
deleted file mode 100644
index a6120f1845..0000000000
--- a/board/freescale/c29xpcie/README
+++ /dev/null
@@ -1,99 +0,0 @@
-Overview
-=========
-C29XPCIE board is a series of Freescale PCIe add-in cards to perform
-as public key crypto accelerator or secure key management module.
-It includes C293PCIE board, C293PCIE board and C291PCIE board.
-The Freescale C29x family is a high performance crypto co-processor.
-It combines a single e500v2 core with necessary SEC engines.
-(maximum core frequency 1000/1200 MHz).
-
-The C29xPCIE board features are as follows:
-Memory subsystem:
-	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
-	- 64 Mbyte NOR flash single-chip memory
-	- 4 Gbyte NAND flash memory
-	- 1 Mbit AT24C1024 I2C EEPROM
-	- 16 Mbyte SPI memory
-
-Interfaces:
-	- 10/100/1000 BaseT Ethernet ports:
-		- eTSEC1, RGMII: one 10/100/1000 port
-		- eTSEC2, RGMII: one 10/100/1000 port
-	- DUART interface:
-		- DUART interface: supports two UARTs up to 115200 bps for
-		   console display
-
-Board connectors:
-	- Mini-ITX power supply connector
-	- JTAG/COP for debugging
-
-Physical Memory Map on C29xPCIE
-===============================
-Address Start   Address End   Memory type
-0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
-0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
-0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
-0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
-0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
-0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
-0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR
-
-Serial Port Configuration on C29xPCIE
-=====================================
-Configure the serial port of the attached computer with the following values:
-	-Data rate: 115200 bps
-	-Number of data bits: 8
-	-Parity: None
-	-Number of Stop bits: 1
-	-Flow Control: Hardware/None
-
-Settings of DIP-switch
-======================
-  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
-  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
-Note: 1 stands for 'off', 0 stands for 'on'
-
-Build and program U-Boot to NOR flash
-==================================
-1. Build u-boot.bin image example:
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make C293PCIE
-
-2. Program u-boot.bin into NOR flash
-	=> tftp $loadaddr $uboot
-	=> protect off eff40000 +$filesize
-	=> erase eff40000 +$filesize
-	=> cp.b $loadaddr eff40000 $filesize
-
-3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
-
-Alternate NOR bank
-==================
-There are four banks in C29XPCIE board, example to change bank booting:
-1. Program u-boot.bin into alternate NOR bank
-	=> tftp $loadaddr $uboot
-	=> protect off e9f40000 +$filesize
-	=> erase e9f40000 +$filesize
-	=> cp.b $loadaddr e9f40000 $filesize
-
-2. Switch to alternate NOR bank
-	=> cpld_cmd reset altbank [bank]
-	- [bank] bank value select 1-4
-	- bank 1 on the flash 0x0000000~0x0ffffff
-	- bank 2 on the flash 0x1000000~0x1ffffff
-	- bank 3 on the flash 0x2000000~0x2ffffff
-	- bank 4 on the flash 0x3000000~0x3ffffff
-	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
-
-Build and program U-Boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
-	make C29xPCIE_SPIFLASH_config; make
-	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
-
-2. Program u-boot-spi.bin into SPI flash
-	=> tftp $loadaddr $uboot-spi
-	=> sf erase 0 100000
-	=> sf write $loadaddr 0 $filesize
-
-3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
deleted file mode 100644
index 74502c6d18..0000000000
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <pci.h>
-#include <fsl_ifc.h>
-#include <asm/fsl_pci.h>
-
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	struct cpu_type *cpu = gd->arch.cpu;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
-	printf("Board: %sPCIe, ", cpu->name);
-	printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-
-	/* Clock configuration to access CPLD using IFC(GPCM) */
-	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 1;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_64M, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-	/* Register 1G MDIO bus */
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_del_sec(void *blob, int offset)
-{
-	int nodeoff = 0;
-
-	while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
-			CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
-			+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
-		fdt_del_node(blob, nodeoff);
-		offset++;
-	}
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-	struct cpu_type *cpu;
-
-	cpu = gd->arch.cpu;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-#if defined(CONFIG_PCI)
-	FT_FSL_PCI_SETUP;
-#endif
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-	if (cpu->soc_ver == SVR_C291)
-		fdt_del_sec(blob, 1);
-	else if (cpu->soc_ver == SVR_C292)
-		fdt_del_sec(blob, 2);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
deleted file mode 100644
index 826af428ce..0000000000
--- a/board/freescale/c29xpcie/cpld.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- *         Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
- * CPLD register map
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#include "cpld.h"
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(u8 banksel)
-{
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-	u8 reg11;
-
-	reg11 = in_8(&cpld_data->flhcsr);
-
-	switch (banksel) {
-	case 1:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
-			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
-		break;
-	case 2:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
-			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
-		break;
-	case 3:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
-			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
-		break;
-	case 4:
-		out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
-			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
-		break;
-	default:
-		printf("Invalid value! [1-4]\n");
-		return;
-	}
-
-	udelay(100);
-	do_reset(NULL, 0, 0, NULL);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
-	cpld_set_altbank(4);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
-	printf("chipid1		= 0x%02x\n", in_8(&cpld_data->chipid1));
-	printf("chipid2		= 0x%02x\n", in_8(&cpld_data->chipid2));
-	printf("hwver		= 0x%02x\n", in_8(&cpld_data->hwver));
-	printf("cpldver		= 0x%02x\n", in_8(&cpld_data->cpldver));
-	printf("rstcon		= 0x%02x\n", in_8(&cpld_data->rstcon));
-	printf("flhcsr		= 0x%02x\n", in_8(&cpld_data->flhcsr));
-	printf("wdcsr		= 0x%02x\n", in_8(&cpld_data->wdcsr));
-	printf("wdkick		= 0x%02x\n", in_8(&cpld_data->wdkick));
-	printf("fancsr		= 0x%02x\n", in_8(&cpld_data->fancsr));
-	printf("ledcsr		= 0x%02x\n", in_8(&cpld_data->ledcsr));
-	printf("misc		= 0x%02x\n", in_8(&cpld_data->misccsr));
-	printf("bootor		= 0x%02x\n", in_8(&cpld_data->bootor));
-	printf("bootcfg1	= 0x%02x\n", in_8(&cpld_data->bootcfg1));
-	printf("bootcfg2	= 0x%02x\n", in_8(&cpld_data->bootcfg2));
-	printf("bootcfg3	= 0x%02x\n", in_8(&cpld_data->bootcfg3));
-	printf("bootcfg4	= 0x%02x\n", in_8(&cpld_data->bootcfg4));
-	putc('\n');
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	int rc = 0;
-	unsigned char value;
-
-	if (argc <= 1)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "reset") == 0) {
-		if (!strcmp(argv[2], "altbank") && argv[3]) {
-			value = (u8)simple_strtoul(argv[3], NULL, 16);
-			cpld_set_altbank(value);
-		} else if (!argv[2])
-			cpld_set_defbank();
-		else
-			cmd_usage(cmdtp);
-#ifdef DEBUG
-	} else if (strcmp(argv[1], "dump") == 0) {
-		cpld_dump_regs();
-#endif
-	} else
-		rc = cmd_usage(cmdtp);
-
-	return rc;
-}
-
-U_BOOT_CMD(
-	cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
-	"Reset the board using the CPLD sequencer",
-	"reset - hard reset to default bank 4\n"
-	"cpld_cmd reset altbank [bank]- reset to alternate bank\n"
-	"	- [bank] bank value select 1-4\n"
-	"	- bank 1 on the flash 0x0000000~0x0ffffff\n"
-	"	- bank 2 on the flash 0x1000000~0x1ffffff\n"
-	"	- bank 3 on the flash 0x2000000~0x2ffffff\n"
-	"	- bank 4 on the flash 0x3000000~0x3ffffff\n"
-#ifdef DEBUG
-	"cpld_cmd dump - display the CPLD registers\n"
-#endif
-	);
-#endif
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
deleted file mode 100644
index 02e9160854..0000000000
--- a/board/freescale/c29xpcie/cpld.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2013 Freescale Semiconductor
- * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
- *         Po Liu <Po.Liu@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
-	u8 chipid1;	/* 0x0 - CPLD Chip ID1 Register */
-	u8 chipid2;	/* 0x1 - CPLD Chip ID2 Register */
-	u8 hwver;	/* 0x2 - Hardware Version Register */
-	u8 cpldver;	/* 0x3 - Software Version Register */
-	u8 res[12];
-	u8 rstcon;	/* 0x10 - Reset control register */
-	u8 flhcsr;	/* 0x11 - Flash control and status Register */
-	u8 wdcsr;	/* 0x12 - Watchdog control and status Register */
-	u8 wdkick;	/* 0x13 - Watchdog kick Register */
-	u8 fancsr;	/* 0x14 - Fan control and status Register */
-	u8 ledcsr;	/* 0x15 - LED control and status Register */
-	u8 misccsr;	/* 0x16 - Misc control and status Register */
-	u8 bootor;	/* 0x17 - Boot configure override Register */
-	u8 bootcfg1;	/* 0x18 - Boot configure 1 Register */
-	u8 bootcfg2;	/* 0x19 - Boot configure 2 Register */
-	u8 bootcfg3;	/* 0x1a - Boot configure 3 Register */
-	u8 bootcfg4;	/* 0x1b - Boot configure 4 Register */
-};
-
-#define CPLD_BANKSEL_EN		0x02
-#define CPLD_BANKSEL_MASK	0x3f
-#define CPLD_SELECT_BANK1	0xc0
-#define CPLD_SELECT_BANK2	0x80
-#define CPLD_SELECT_BANK3	0x40
-#define CPLD_SELECT_BANK4	0x00
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
deleted file mode 100644
index 5795a27f65..0000000000
--- a/board/freescale/c29xpcie/ddr.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include "cpld.h"
-
-#define C29XPCIE_HARDWARE_REVA	0x40
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 536870912u,
-	.capacity = 536870912u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 8,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 14,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 2,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1650,
-	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
-	.taa_ps = 14050,
-	.twr_ps = 15000,
-	.trcd_ps = 13500,
-	.trrd_ps = 75000,
-	.trp_ps = 13500,
-	.tras_ps = 40000,
-	.trc_ps = 49500,
-	.trfc_ps = 160000,
-	.twtr_ps = 75000,
-	.trtp_ps = 75000,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 30000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-	int i;
-
-	popts->clk_adjust = 4;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 4;
-	popts->half_strength_driver_enable = 1;
-	popts->bstopre = 0x3cf;
-	popts->quad_rank_present = 1;
-	popts->rtt_override = 1;
-	popts->rtt_override_value = 1;
-	popts->dynamic_power = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x4;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
-		popts->ecc_mode = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
-
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
-	int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
-				sizeof(generic_spd_eeprom_t));
-
-	if (ret) {
-		printf("DDR: failed to read SPD from address %u\n",
-				i2c_address);
-		memset(spd, 0, sizeof(generic_spd_eeprom_t));
-	}
-}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
deleted file mode 100644
index 6d441d87a7..0000000000
--- a/board/freescale/c29xpcie/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
-					LAW_TRGT_IF_PLATFORM_SRAM),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
deleted file mode 100644
index 421c2d4b1f..0000000000
--- a/board/freescale/c29xpcie/spl.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
-	bd_t *bd;
-
-	memset(gd, 0, sizeof(gd_t));
-	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-	/* relocate environment function pointers etc. */
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-
-	i2c_init_all();
-
-	dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	puts("TPL\n");
-#else
-	puts("SPL\n");
-#endif
-
-	nand_boot();
-}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
deleted file mode 100644
index 8193afdf6a..0000000000
--- a/board/freescale/c29xpcie/spl_minimal.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot...\n");
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	puts("SPL\n");
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
deleted file mode 100644
index ef844a0b3d..0000000000
--- a/board/freescale/c29xpcie/tlb.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-			0, 1, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 2, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 3, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_64K, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_64K, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
-			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 6, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
-			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 7, BOOKE_PAGESZ_256K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
-		(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
-			CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-			0, 8, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-			CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-			0, 9, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig
deleted file mode 100644
index 1a6a9d4598..0000000000
--- a/board/freescale/mpc8536ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8536DS
-
-config SYS_BOARD
-	default "mpc8536ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8536DS"
-
-endif
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
deleted file mode 100644
index 5ce5164e49..0000000000
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8536DS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8536ds/
-F:	include/configs/MPC8536DS.h
-F:	configs/MPC8536DS_defconfig
-F:	configs/MPC8536DS_36BIT_defconfig
-F:	configs/MPC8536DS_SDCARD_defconfig
-F:	configs/MPC8536DS_SPIFLASH_defconfig
diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile
deleted file mode 100644
index 6b936aa299..0000000000
--- a/board/freescale/mpc8536ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8536ds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README
deleted file mode 100644
index 2a38bd6dda..0000000000
--- a/board/freescale/mpc8536ds/README
+++ /dev/null
@@ -1,127 +0,0 @@
-Overview:
-=========
-
-The MPC8536E integrates a PowerPC processor core with system logic
-required for imaging, networking, and communications applications.
-
-Boot from NAND:
-===============
-
-The MPC8536E is capable of booting from NAND flash which uses the image
-u-boot-nand.bin. This image contains two parts: a first stage image(also
-call 4K NAND loader and a second stage image. The former is appended to
-the latter to produce u-boot-nand.bin.
-
-The bootup process can be divided into two stages: the first stage will
-configure the L2SRAM, then copy the second stage image to L2SRAM and jump
-to it. The second stage image is to configure all the hardware and boot up
-to U-Boot command line.
-
-The 4K NAND loader's code comes from the corresponding nand_spl directory,
-along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
-is mainly used to shrink the code size to the 4K size limitation.
-
-The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
-second stage image. It's set in the board config file when boot from NAND
-is selected.
-
-Build and boot steps
---------------------
-
-1. Building image
-	make MPC8536DS_NAND_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 1011
-	SW9[1-3] = 101
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-3. Flash image
-	tftp 1000000 u-boot-nand.bin
-	nand erase 0 a0000
-	nand write 1000000 0 a0000
-
-Boot from On-chip ROM:
-======================
-
-The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
-and boot from eSPI. When power on, the porcessor excutes the ROM code to
-initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
-the memory device that interfaced to the controller, such as the SDCard or
-SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
-
-The memory device should contain a specific data structure with control word
-and config word at the fixed address. The config word direct the process how
-to config the memory device, and the control word direct the processor where
-to find the image on the memory device, or where copy the main image to. The
-user can use any method to store the data structure to the memory device, only
-if store it on the assigned address.
-
-Build and boot steps
---------------------
-
-For boot from eSDHC:
-1. Build image
-	make MPC8536DS_SDCARD_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 0111
-	SW3[1]   = 0
-	SW8[7]   = 0 - The on-board SD/MMC slot is active
-	SW8[7]   = 1 - The externel SD/MMC slot is active
-
-3. Put image to SDCard
-	Put the follwing info at the assigned address on the SDCard:
-
-	   Offset   |   Data     | Description
-	--------------------------------------------------------
-	| 0x40-0x43 | 0x424F4F54 | BOOT signature              |
-	--------------------------------------------------------
-	| 0x48-0x4B | 0x00080000 | u-boot.bin's size           |
-	--------------------------------------------------------
-	| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
-	--------------------------------------------------------
-	| 0x58-0x5B | 0xF8F80000 | Target Address              |
-	-------------------------------------------------------
-	| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address  |
-	--------------------------------------------------------
-	| 0x68-0x6B | 0x6        | Number of Config Addr/Data  |
-	--------------------------------------------------------
-	| 0x80-0x83 | 0xFF720100 | Config Addr 1               |
-	| 0x84-0x87 | 0xF8F80000 | Config Data 1               |
-	--------------------------------------------------------
-	| 0x88-0x8b | 0xFF720e44 | Config Addr 2               |
-	| 0x8c-0x8f | 0x0000000C | Config Data 2               |
-	--------------------------------------------------------
-	| 0x90-0x93 | 0xFF720000 | Config Addr 3               |
-	| 0x94-0x97 | 0x80010000 | Config Data 3               |
-	--------------------------------------------------------
-	| 0x98-0x9b | 0xFF72e40c | Config Addr 4               |
-	| 0x9c-0x9f | 0x00000040 | Config Data 4               |
-	--------------------------------------------------------
-	| 0xa0-0xa3 | 0x40000001 | Config Addr 5               |
-	| 0xa4-0xa7 | 0x00000100 | Config Data 5               |
-	--------------------------------------------------------
-	| 0xa8-0xab | 0x80000001 | Config Addr 6               |
-	| 0xac-0xaf | 0x80000001 | Config Data 6               |
-	--------------------------------------------------------
-	|              ......                                  |
-	--------------------------------------------------------
-	| 0x???????? | u-boot.bin                              |
-	--------------------------------------------------------
-
-	then insert the SDCard to the active slot to boot up.
-
-For boot from eSPI:
-1. Build image
-	make MPC8536DS_SPIFLASH_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 0110
-
-3. Put image to SPI flash
-	Put the info in the above table onto the SPI flash, then
-	boot up.
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
deleted file mode 100644
index 8319ae8245..0000000000
--- a/board/freescale/mpc8536ds/ddr.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-
-	/*
-	 * For wake up arp feature, we need enable auto self refresh
-	 */
-	popts->auto_self_refresh_en = 1;
-	popts->sr_it = 0x6;
-}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
deleted file mode 100644
index d59b12d82c..0000000000
--- a/board/freescale/mpc8536ds/law.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
deleted file mode 100644
index 5907a7b428..0000000000
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ /dev/null
@@ -1,293 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <spd.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <spd_sdram.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-#include <sata.h>
-
-#include "../common/sgmii_riser.h"
-
-int board_early_init_f (void)
-{
-#ifdef CONFIG_MMC
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	setbits_be32(&gur->pmuxcr,
-			(MPC85xx_PMUXCR_SDHC_CD |
-			 MPC85xx_PMUXCR_SDHC_WP));
-
-	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
-	 * however, this erratum only applies to MPC8536 Rev1.0.
-	 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
-	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
-			(SVR_MIN(get_svr()) >= 0x1))
-			|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
-		setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
-#endif
-	return 0;
-}
-
-int checkboard (void)
-{
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf("Board: MPC8536DS Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
-		case PIXIS_VBOOT_LBMAP_NOR0:
-			puts ("vBank: 0\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR1:
-			puts ("vBank: 1\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR2:
-			puts ("vBank: 2\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR3:
-			puts ("vBank: 3\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_PJET:
-			puts ("Promjet\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NAND:
-			puts ("NAND\n");
-			break;
-	}
-
-	return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
-	uint d_init;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
-	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
-	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
-	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
-		udelay(1000);
-	}
-	debug("DDR: memory initialized\n\n");
-	asm("sync; isync");
-	udelay(500);
-#endif
-
-	return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno;
-
-	first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-
-	pci_speed = 66666000;
-	pci_32 = 1;
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 1;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].phyaddr = 0;
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (is_serdes_configured(SGMII_TSEC3)) {
-		puts("eTSEC3 is in sgmii mode.\n");
-		tsec_info[num].phyaddr = 1;
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	if (is_serdes_configured(SGMII_TSEC1) ||
-	    is_serdes_configured(SGMII_TSEC3)) {
-		fsl_sgmii_riser_init(tsec_info, num);
-	}
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-#ifdef CONFIG_HAS_FSL_MPH_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
deleted file mode 100644
index 5df4788e0a..0000000000
--- a/board/freescale/mpc8536ds/tlb.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-
-	/* W**G* - Flash/promjet, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256K, 1),
-
-	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig
deleted file mode 100644
index f1792de8e3..0000000000
--- a/board/freescale/p1022ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1022DS
-
-config SYS_BOARD
-	default "p1022ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P1022DS"
-
-endif
diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS
deleted file mode 100644
index 62256c3703..0000000000
--- a/board/freescale/p1022ds/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-P1022DS BOARD
-M:	Timur Tabi <timur@tabi.org>
-S:	Maintained
-F:	board/freescale/p1022ds/
-F:	include/configs/P1022DS.h
-F:	configs/P1022DS_defconfig
-F:	configs/P1022DS_36BIT_defconfig
-F:	configs/P1022DS_36BIT_NAND_defconfig
-F:	configs/P1022DS_36BIT_SDCARD_defconfig
-F:	configs/P1022DS_36BIT_SPIFLASH_defconfig
-F:	configs/P1022DS_NAND_defconfig
-F:	configs/P1022DS_SDCARD_defconfig
-F:	configs/P1022DS_SPIFLASH_defconfig
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
deleted file mode 100644
index 699e5b5288..0000000000
--- a/board/freescale/p1022ds/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-endif
-obj-y	+= p1022ds.o
-obj-y	+= ddr.o
-obj-$(CONFIG_FSL_DIU_FB) += diu.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README
deleted file mode 100644
index 04d9197074..0000000000
--- a/board/freescale/p1022ds/README
+++ /dev/null
@@ -1,23 +0,0 @@
-Overview
---------
-P1022ds is a Low End Dual core platform supporting the P1022 processor
-of QorIQ series. P1022 is an e500 based dual core SOC.
-
-
-Pin Multiplex(hwconfig setting)
--------------------------------
-Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
-via hwconfig, i.e:
-'setenv hwconfig usb2' to enable USB2 and disable eTsec2
-'setenv hwconfig tdm' to enable TDM and disable Audio
-'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
- and disable TDM
-'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
-'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
- is 11MHz), disable eTsec2 and TDM
-
-Warning: TDM and AUDIO can not enable simultaneous !
-and AUDIO codec clock sources only setting as 11MHz or 12MHz !
-'setenv hwconfig 'audclk:12;tdm'	--- error !
-'setenv hwconfig 'audclk:11;tdm'	--- error !
-'setenv hwconfig 'audclk:10'		--- error !
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
deleted file mode 100644
index 70932115f4..0000000000
--- a/board/freescale/p1022ds/ddr.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;		/* Range: 0-8 */
-	u32 cpo;		/* Range: 2-31 */
-	u32 write_data_delay;	/* Range: 0-6 */
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters dimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{1,  549,    5,  31,     3, 0},
-	{1,  850,    5,  31,     5, 0},
-	{2,  549,    5,  31,     3, 0},
-	{2,  850,    5,  31,     5, 0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned long ddr_freq;
-	unsigned int i;
-
-
-	if (ctrl_num) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	/* set odt_rd_cfg and odt_wr_cfg. */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = 0;
-		popts->cs_local_opts[i].odt_wr_cfg = 1;
-	}
-
-	pbsp = dimm0;
-	/*
-	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp->clk_adjust;
-		popts->cpo_override = pbsp->cpo;
-		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twot_en = pbsp->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	popts->half_strength_driver_enable = 1;
-
-	/* Per AN4039, enable ZQ calibration. */
-	popts->zq_en = 1;
-
-	/*
-	 * For wake-up on ARP, we need auto self refresh enabled
-	 */
-	popts->auto_self_refresh_en = 1;
-	popts->sr_it = 0xb;
-}
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
deleted file mode 100644
index 918b4b9f6a..0000000000
--- a/board/freescale/p1022ds/diu.c
+++ /dev/null
@@ -1,478 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Authors: Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include "../common/ngpixis.h"
-#include <fsl_diu_fb.h>
-
-/* The CTL register is called 'csr' in the ngpixis_t structure */
-#define PX_CTL_ALTACC		0x80
-
-#define PX_BRDCFG0_ELBC_SPI_MASK	0xc0
-#define PX_BRDCFG0_ELBC_SPI_ELBC	0x00
-#define PX_BRDCFG0_ELBC_SPI_NULL	0xc0
-#define PX_BRDCFG0_ELBC_DIU		0x02
-
-#define PX_BRDCFG1_DVIEN	0x80
-#define PX_BRDCFG1_DFPEN	0x40
-#define PX_BRDCFG1_BACKLIGHT	0x20
-
-#define PMUXCR_ELBCDIU_MASK	0xc0000000
-#define PMUXCR_ELBCDIU_NOR16	0x80000000
-#define PMUXCR_ELBCDIU_DIU	0x40000000
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register.  So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-/*
- * Variables used by the DIU/LBC switching code.  It's safe to makes these
- * global, because the DIU requires DDR, so we'll only run this code after
- * relocation.
- */
-static u8 px_brdcfg0;
-static u32 pmuxcr;
-static void *lbc_lcs0_ba;
-static void *lbc_lcs1_ba;
-static u32 old_br0, old_or0, old_br1, old_or1;
-static u32 new_br0, new_or0, new_br1, new_or1;
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	debug("DIU pixval = %u\n", pixval);
-
-	/* Modify PXCLK in GUTS CLKDVDR */
-	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
-	out_be32(&gur->clkdvdr, temp);			/* turn off clock */
-	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	const char *name;
-	u32 pixel_format;
-	u8 temp;
-	phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
-
-	/*
-	 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
-	 * otherwise writes to these addresses won't actually appear on the
-	 * local bus, and so the PIXIS won't see them.
-	 *
-	 * In FCM mode, writes go to the NAND controller, which does not pass
-	 * them to the localbus directly.  So we force BR0 and BR1 into GPCM
-	 * mode, since we don't care about what's behind the localbus any
-	 * more.  However, we save those registers first, so that we can
-	 * restore them when necessary.
-	 */
-	new_br0 = old_br0 = get_lbc_br(0);
-	new_br1 = old_br1 = get_lbc_br(1);
-	new_or0 = old_or0 = get_lbc_or(0);
-	new_or1 = old_or1 = get_lbc_or(1);
-
-	/*
-	 * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
-	 * force the values to simple 32KB GPCM windows with the most
-	 * conservative timing.
-	 */
-	if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
-		new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
-		new_or0 = OR_AM_32KB | 0xFF7;
-		set_lbc_br(0, new_br0);
-		set_lbc_or(0, new_or0);
-	}
-	if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
-		new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
-		new_or1 = OR_AM_32KB | 0xFF7;
-		set_lbc_br(1, new_br1);
-		set_lbc_or(1, new_or1);
-	}
-
-	/*
-	 * Determine the physical addresses for Chip Selects 0 and 1.  The
-	 * BR0/BR1 registers contain the truncated physical addresses for the
-	 * chip selects, mapped via the localbus LAW.  Since the BRx registers
-	 * only contain the lower 32 bits of the address, we have to determine
-	 * the upper 4 bits some other way.  The proper way is to scan the LAW
-	 * table looking for a matching localbus address. Instead, we cheat.
-	 * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
-	 * 36-bit addressing.
-	 */
-#ifdef CONFIG_PHYS_64BIT
-	phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
-	phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
-#else
-	phys0 = old_br0 & old_or0 & BR_BA;
-	phys1 = old_br1 & old_or1 & BR_BA;
-#endif
-
-	 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
-	lbc_lcs0_ba = map_physmem(phys0, 1, 0);
-	lbc_lcs1_ba = map_physmem(phys1, 1, 0);
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	temp = in_8(&pixis->brdcfg1);
-
-	if (strncmp(port, "lvds", 4) == 0) {
-		/* Single link LVDS */
-		temp &= ~PX_BRDCFG1_DVIEN;
-		/*
-		 * LVDS also needs backlight enabled, otherwise the display
-		 * will be blank.
-		 */
-		temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
-		name = "Single-Link LVDS";
-	} else {	/* DVI */
-		/* Enable the DVI port, disable the DFP and the backlight */
-		temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
-		temp |= PX_BRDCFG1_DVIEN;
-		name = "DVI";
-	}
-
-	printf("DIU:   Switching to %s monitor @ %ux%u\n", name, xres, yres);
-	out_8(&pixis->brdcfg1, temp);
-
-	/*
-	 * Enable PIXIS indirect access mode.  This is a hack that allows us to
-	 * access PIXIS registers even when the LBC pins have been muxed to the
-	 * DIU.
-	 */
-	setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
-	/*
-	 * Route the LAD pins to the DIU.  This will disable access to the eLBC,
-	 * which means we won't be able to read/write any NOR flash addresses!
-	 */
-	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-	px_brdcfg0 = in_8(lbc_lcs1_ba);
-	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
-	in_8(lbc_lcs1_ba);
-
-	/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
-	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
-	pmuxcr = in_be32(&gur->pmuxcr);
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
-
-/*
- * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
- *
- * On the Freescale P1022, the DIU video signal and the LBC address/data lines
- * share the same pins, which means that when the DIU is active (e.g. the
- * console is on the DVI display), NOR flash cannot be accessed.  So we use the
- * weak accessor feature of the CFI flash code to temporarily switch the pin
- * mux from DIU to LBC whenever we want to read or write flash.  This has a
- * significant performance penalty, but it's the only way to make it work.
- *
- * There are two muxes: one on the chip, and one on the board. The chip mux
- * controls whether the pins are used for the DIU or the LBC, and it is
- * set via PMUXCR.  The board mux controls whether those signals go to
- * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
- */
-static int set_mux_to_lbc(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Switch the muxes only if they're currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		/*
-		 * In DIU mode, the PIXIS can only be accessed indirectly
-		 * since we can't read/write the LBC directly.
-		 */
-		/* Set the board mux to LBC.  This will disable the display. */
-		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-		out_8(lbc_lcs1_ba, px_brdcfg0);
-		in_8(lbc_lcs1_ba);
-
-		/* Disable indirect PIXIS mode */
-		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
-		clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
-
-		/* Set the chip mux to LBC mode, so that writes go to flash. */
-		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
-			 PMUXCR_ELBCDIU_NOR16);
-		in_be32(&gur->pmuxcr);
-
-		/* Restore the BR0 and BR1 settings */
-		set_lbc_br(0, old_br0);
-		set_lbc_or(0, old_or0);
-		set_lbc_br(1, old_br1);
-		set_lbc_or(1, old_or1);
-
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * set_mux_to_diu - re-enable the DIU muxing
- *
- * This function restores the chip and board muxing to point to the DIU.
- */
-static void set_mux_to_diu(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Set BR0 and BR1 to GPCM mode */
-	set_lbc_br(0, new_br0);
-	set_lbc_or(0, new_or0);
-	set_lbc_br(1, new_br1);
-	set_lbc_or(1, new_or1);
-
-	/* Enable indirect PIXIS mode */
-	setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
-	/* Set the board mux to DIU.  This will enable the display. */
-	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
-	in_8(lbc_lcs1_ba);
-
-	/* Set the chip mux to DIU mode. */
-	out_be32(&gur->pmuxcr, pmuxcr);
-	in_be32(&gur->pmuxcr);
-}
-
-/*
- * pixis_read - board-specific function to read from the PIXIS
- *
- * This function overrides the generic pixis_read() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-u8 pixis_read(unsigned int reg)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Use indirect mode if the mux is currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		out_8(lbc_lcs0_ba, reg);
-		return in_8(lbc_lcs1_ba);
-	} else {
-		void *p = (void *)PIXIS_BASE;
-
-		return in_8(p + reg);
-	}
-}
-
-/*
- * pixis_write - board-specific function to write to the PIXIS
- *
- * This function overrides the generic pixis_write() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-void pixis_write(unsigned int reg, u8 value)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Use indirect mode if the mux is currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		out_8(lbc_lcs0_ba, reg);
-		out_8(lbc_lcs1_ba, value);
-		/* Do a read-back to ensure the write completed */
-		in_8(lbc_lcs1_ba);
-	} else {
-		void *p = (void *)PIXIS_BASE;
-
-		out_8(p + reg, value);
-	}
-}
-
-void pixis_bank_reset(void)
-{
-	/*
-	 * For some reason, a PIXIS bank reset does not work if the PIXIS is
-	 * in indirect mode, so switch to direct mode first.
-	 */
-	set_mux_to_lbc();
-
-	out_8(&pixis->vctl, 0);
-	out_8(&pixis->vctl, 1);
-
-	while (1);
-}
-
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-void flash_write8(u8 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writeb(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write16(u16 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writew(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write32(u32 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writel(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write64(u64 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-	uint32_t *p = addr;
-
-	/*
-	 * There is no __raw_writeq(), so do the write manually.  We don't trust
-	 * the compiler, so we use inline assembly.
-	 */
-	__asm__ __volatile__(
-		"stw%U0%X0 %2,%0;\n"
-		"stw%U1%X1 %3,%1;\n"
-		: "=m" (*p), "=m" (*(p + 1))
-		: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
-
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.  We
-		 * read addr+4 because we just wrote to addr+4, so that's how we
-		 * maintain execution order.  set_mux_to_diu() includes a sync
-		 * that will ensure the __raw_readb() completes before it
-		 * switches the mux.
-		 */
-		__raw_readb(addr + 4);
-		set_mux_to_diu();
-	}
-}
-
-u8 flash_read8(void *addr)
-{
-	u8 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readb(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u16 flash_read16(void *addr)
-{
-	u16 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readw(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u32 flash_read32(void *addr)
-{
-	u32 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readl(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u64 flash_read64(void *addr)
-{
-	u64 ret;
-
-	int sw = set_mux_to_lbc();
-
-	/* There is no __raw_readq(), so do the read manually */
-	ret = *(volatile u64 *)addr;
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-#endif
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
deleted file mode 100644
index 079095d008..0000000000
--- a/board/freescale/p1022ds/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
deleted file mode 100644
index d10160d17a..0000000000
--- a/board/freescale/p1022ds/p1022ds.c
+++ /dev/null
@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-#include "../common/ngpixis.h"
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Set pmuxcr to allow both i2c1 and i2c2 */
-	setbits_be32(&gur->pmuxcr, 0x1000);
-#ifdef CONFIG_SYS_RAMBOOT
-	setbits_be32(&gur->pmuxcr,
-		in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-#endif
-
-	/* Read back the register to synchronize the write. */
-	in_be32(&gur->pmuxcr);
-
-	/* Set the pin muxing to enable ETSEC2. */
-	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
-
-	/* Enable the SPI */
-	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	u8 sw;
-
-	printf("Board: P1022DS Sys ID: 0x%02x, "
-	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
-	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
-
-	switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
-	case 0:
-		printf ("vBank: %u\n", ((sw & 0x30) >> 4));
-		break;
-	case 1:
-		printf ("NAND\n");
-		break;
-	case 2:
-	case 3:
-		puts ("Promjet\n");
-		break;
-	}
-
-	return 0;
-}
-
-#define CONFIG_TFP410_I2C_ADDR	0x38
-
-/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK	0x0c
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK	0x03
-
-/* Route the I2C1 pins to the SSI port instead. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI	0x08
-
-/* Choose the 12.288Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12		0x02
-
-/* Choose the 11.2896Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11		0x01
-
-/* Connect to USB2 */
-#define CONFIG_PIXIS_BRDCFG0_USB2		0x10
-/* Connect to TFM bus */
-#define CONFIG_PIXIS_BRDCFG1_TDM		0x0c
-/* Connect to SPI */
-#define CONFIG_PIXIS_BRDCFG0_SPI		0x80
-
-int misc_init_r(void)
-{
-	u8 temp;
-	const char *audclk;
-	size_t arglen;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	/* For DVI, enable the TFP410 Encoder. */
-
-	temp = 0xBF;
-	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	debug("DVI Encoder Read: 0x%02x\n", temp);
-
-	temp = 0x10;
-	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	debug("DVI Encoder Read: 0x%02x\n",temp);
-
-	/* Enable the USB2 in PMUXCR2 and FGPA */
-	if (hwconfig("usb2")) {
-		clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
-			MPC85xx_PMUXCR2_USB);
-		setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
-	}
-
-	/* tdm and audio can not enable simultaneous*/
-	if (hwconfig("tdm") && hwconfig("audclk")){
-		printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
-		return -1;
-	}
-
-	/* Enable the TDM in PMUXCR and FGPA */
-	if (hwconfig("tdm")) {
-		clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
-			MPC85xx_PMUXCR_TDM);
-		setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
-		/* TDM need some configration option by SPI */
-		clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
-			MPC85xx_PMUXCR_SPI);
-		setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
-	}
-
-	/*
-	 * Enable the reference clock for the WM8776 codec, and route the MUX
-	 * pins for SSI. The default is the 12.288 MHz clock
-	 */
-
-	if (hwconfig("audclk")) {
-		temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
-			CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
-		temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
-		audclk = hwconfig_arg("audclk", &arglen);
-		/* Check the first two chars only */
-		if (audclk && (strncmp(audclk, "11", 2) == 0))
-			temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
-		else
-			temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
-		setbits_8(&pixis->brdcfg1, temp);
-	}
-
-	return 0;
-}
-
-/*
- * A list of PCI and SATA slots
- */
-enum slot_id {
-	SLOT_PCIE1 = 1,
-	SLOT_PCIE2,
-	SLOT_PCIE3,
-	SLOT_PCIE4,
-	SLOT_PCIE5,
-	SLOT_SATA1,
-	SLOT_SATA2
-};
-
-/*
- * This array maps the slot identifiers to their names on the P1022DS board.
- */
-static const char *slot_names[] = {
-	[SLOT_PCIE1] = "Slot 1",
-	[SLOT_PCIE2] = "Slot 2",
-	[SLOT_PCIE3] = "Slot 3",
-	[SLOT_PCIE4] = "Slot 4",
-	[SLOT_PCIE5] = "Mini-PCIe",
-	[SLOT_SATA1] = "SATA 1",
-	[SLOT_SATA2] = "SATA 2",
-};
-
-/*
- * This array maps a given SERDES configuration and SERDES device to the PCI or
- * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
- */
-static u8 serdes_dev_slot[][SATA2 + 1] = {
-	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
-	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
-		   [PCIE2] = SLOT_PCIE5 },
-	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-		   [PCIE2] = SLOT_PCIE3,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-		   [PCIE2] = SLOT_PCIE3 },
-	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
-		   [PCIE2] = SLOT_PCIE3,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x1c] = { [PCIE1] = SLOT_PCIE1,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
-	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
-};
-
-
-/*
- * Returns the name of the slot to which the PCIe or SATA controller is
- * connected
- */
-const char *board_serdes_name(enum srds_prtcl device)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
-	const char *name = slot_names[slot];
-
-	if (name)
-		return name;
-	else
-		return "Nothing";
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	return 0;
-}
-
-/*
- * Initialize on-board and/or PCI Ethernet devices
- *
- * Returns:
- *      <0, error
- *       0, no ethernet devices found
- *      >0, number of ethernet devices initialized
- */
-int board_eth_init(bd_t *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	unsigned int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/**
- * ft_codec_setup - fix up the clock-frequency property of the codec node
- *
- * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option.  If audclk is not specified, then don't write anything
- * to the device tree, because it means that the codec clock is disabled.
- */
-static void ft_codec_setup(void *blob, const char *compatible)
-{
-	const char *audclk;
-	size_t arglen;
-	u32 freq;
-
-	audclk = hwconfig_arg("audclk", &arglen);
-	if (audclk) {
-		if (strncmp(audclk, "11", 2) == 0)
-			freq = 11289600;
-		else
-			freq = 12288000;
-
-		do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
-				       freq, 1);
-	}
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-	/* Update the WM8776 node's clock frequency property */
-	ft_codec_setup(blob, "wlf,wm8776");
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
deleted file mode 100644
index 39e1bee6f3..0000000000
--- a/board/freescale/p1022ds/spl.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/ngpixis.h"
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
-	66666000, 7499900, 83332500, 8999900,
-	99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
-	int px_spd;
-	u32 plat_ratio, sys_clk, bus_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	console_init_f();
-
-	/* Set pmuxcr to allow both i2c1 and i2c2 */
-	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
-	setbits_be32(&gur->pmuxcr,
-		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
-#ifdef CONFIG_SPL_SPI_BOOT
-	/* Enable the SPI */
-	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-#endif
-
-	/* Read back the register to synchronize the write. */
-	in_be32(&gur->pmuxcr);
-
-	/* initialize selected port with appropriate baud rate */
-	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
-	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	bus_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
-	puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	puts("\nSPI Flash boot...\n");
-#endif
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
-	bd_t *bd;
-
-	memset(gd, 0, sizeof(gd_t));
-	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#ifndef CONFIG_SPL_NAND_BOOT
-	env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-#endif
-	/* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-#else
-	env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C
-	i2c_init_all();
-#else
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
-	puts("Tertiary program loader running in sram...");
-#else
-	puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
deleted file mode 100644
index 31de26318d..0000000000
--- a/board/freescale/p1022ds/spl_minimal.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-
-
-const static u32 sysclk_tbl[] = {
-	66666000, 7499900, 83332500, 8999900,
-	99999000, 11111000, 12499800, 13333200
-};
-
-void board_init_f(ulong bootflag)
-{
-	int px_spd;
-	u32 plat_ratio, sys_clk, bus_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-	/* for FPGA */
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-
-	/* initialize selected port with appropriate baud rate */
-	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
-	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	bus_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-			bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0,
-			CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	puts("\nSecond program loader running in sram...");
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
deleted file mode 100644
index 194fbd5afc..0000000000
--- a/board/freescale/p1022ds/tlb.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* W**G* - Flash/promjet, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
-	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
-	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
-	/* **** - eSDHC/eSPI/NAND boot */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 8, BOOKE_PAGESZ_1G, 1),
-	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE
-	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_16K, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 11, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig
deleted file mode 100644
index 8f9a8d4415..0000000000
--- a/board/freescale/p1_twr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1_TWR
-
-config SYS_BOARD
-	default "p1_twr"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "p1_twr"
-
-endif
diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS
deleted file mode 100644
index 0f9f98f459..0000000000
--- a/board/freescale/p1_twr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-P1_TWR BOARD
-M:	Xiaobo Xie <xiaobo.xie@nxp.com>
-S:	Maintained
-F:	board/freescale/p1_twr/
-F:	include/configs/p1_twr.h
-F:	configs/TWR-P1025_defconfig
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
deleted file mode 100644
index 5e6c658551..0000000000
--- a/board/freescale/p1_twr/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-
-obj-y        += p1_twr.o
-obj-y        += ddr.o
-obj-y        += law.o
-obj-y        += tlb.o
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
deleted file mode 100644
index 85f1f6344a..0000000000
--- a/board/freescale/p1_twr/ddr.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
-	sys_info_t sysinfo;
-	char buf[32];
-	size_t ddr_size;
-	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
-		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
-		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
-		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
-		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
-		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
-		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
-		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
-		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
-		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
-		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
-		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-	};
-
-	get_sys_info(&sysinfo);
-	printf("Configuring DDR for %s MT/s data rate\n",
-			strmhz(buf, sysinfo.freq_ddrbus));
-
-	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
-				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
-		printf("ERROR setting Local Access Windows for DDR\n");
-		return 0;
-	};
-
-	return ddr_size;
-}
diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c
deleted file mode 100644
index 45721f6140..0000000000
--- a/board/freescale/p1_twr/law.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
deleted file mode 100644
index 8e1522a604..0000000000
--- a/board/freescale/p1_twr/p1_twr.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <asm/fsl_serdes.h>
-#include <netdev.h>
-
-#define SYSCLK_64	64000000
-#define SYSCLK_66	66666666
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
-	unsigned int cpdat_val = 0;
-
-	/* Set-up up pin muxing based on board switch settings */
-	cpdat_val = par_io[1].cpdat;
-
-	/* Check switch setting for SYSCLK select (PB3)  */
-	if (cpdat_val & 0x10000000)
-		return SYSCLK_64;
-	else
-		return SYSCLK_66;
-
-	return 0;
-}
-
-#ifdef CONFIG_QE
-
-#define PCA_IOPORT_I2C_ADDR		0x23
-#define PCA_IOPORT_OUTPUT_CMD		0x2
-#define PCA_IOPORT_CFG_CMD		0x6
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
-
-#ifdef CONFIG_TWR_P1025
-	/* GPIO */
-	{1,  0, 1, 0, 0},
-	{1,  18, 1, 0, 0},
-
-	/* GPIO for switch options */
-	{1,  2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
-	{1,  3, 2, 0, 0}, /* SYS_CLK_SELECT */
-	{1,  29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
-	{1,  30, 2, 0, 0}, /* ETH_TDM_SEL */
-
-	/* QE_MUX_MDC */
-	{1,  19, 1, 0, 1}, /* QE_MUX_MDC */
-
-	/* QE_MUX_MDIO */
-	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO */
-
-	/* UCC_1_MII */
-	{0, 23, 2, 0, 2}, /* CLK12 */
-	{0, 24, 2, 0, 1}, /* CLK9 */
-	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
-	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
-	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
-	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
-	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
-	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
-	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
-	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
-	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
-	{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
-	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
-	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
-	{0, 17, 2, 0, 2}, /* ENET1_CRS */
-	{0, 16, 2, 0, 2}, /* ENET1_COL */
-
-	/* UCC_5_RMII */
-	{1, 11, 2, 0, 1}, /* CLK13 */
-	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
-	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
-	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
-	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
-	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
-	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
-	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
-
-	/* TDMA - clock option is configured in OS based on board setting */
-	{1, 23, 2, 0, 2}, /* TDMA_TXD */
-	{1, 25, 2, 0, 2}, /* TDMA_RXD */
-	{1, 26, 1, 0, 2}, /* TDMA_SYNC */
-#endif
-
-	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-#endif
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	setbits_be32(&gur->pmuxcr,
-			(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
-
-	/* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
-	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u8 boot_status;
-
-	printf("Board: %s\n", CONFIG_BOARDNAME);
-
-	boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
-	puts("rom_loc: ");
-	if (boot_status == PORBMSR_ROMLOC_NOR)
-		puts("nor flash");
-	else if (boot_status == PORBMSR_ROMLOC_SDHC)
-		puts("sd");
-	else
-		puts("unknown");
-	puts("\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,           /* perms, wimge */
-		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	ccsr_gur_t *gur __attribute__((unused)) =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	if (is_serdes_configured(SGMII_TSEC2)) {
-		printf("eTSEC2 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-
-#if defined(CONFIG_UEC_ETH)
-	/* QE0 and QE3 need to be exposed for UCC1
-	 * and UCC5 Eth mode (in PMUXCR register).
-	 * Currently QE/LBC muxed pins assumed to be
-	 * LBC for U-Boot and PMUXCR updated by OS if required */
-
-	uec_standard_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_QE)
-static void fdt_board_fixup_qe_pins(void *blob)
-{
-	int node;
-
-	if (!hwconfig("qe")) {
-		/* For QE and eLBC pins multiplexing,
-		 * When don't use QE function, remove
-		 * qe node from dt blob.
-		 */
-		node = fdt_path_offset(blob, "/qe");
-		if (node >= 0)
-			fdt_del_node(blob, node);
-	} else {
-		/* For TWR Peripheral Modules - TWR-SER2
-		 * board only can support Signal Port MII,
-		 * so delete one UEC node when use MII port.
-		 */
-		if (hwconfig("mii"))
-			node = fdt_path_offset(blob, "/qe/ucc@2400");
-		else
-			node = fdt_path_offset(blob, "/qe/ucc@2000");
-		if (node >= 0)
-			fdt_del_node(blob, node);
-	}
-
-	return;
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_QE
-	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
-			sizeof("okay"), 0);
-#endif
-#if defined(CONFIG_TWR_P1025)
-	fdt_board_fixup_qe_pins(blob);
-#endif
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
deleted file mode 100644
index 8e403e3e44..0000000000
--- a/board/freescale/p1_twr/tlb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-			0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* W**G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-			0, 2, BOOKE_PAGESZ_64M, 1),
-
-	/* W**G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_PCI
-	/* *I*G* - PCI memory 1.5G */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O effective: 192K  */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#endif
-
-#ifdef CONFIG_SYS_RAMBOOT
-	/* *I*G - eSDHC boot */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-			0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
index 7881512139..d7f7220063 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -23,6 +23,6 @@ BOOT_FROM sd
  */
 
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 SECURE_BOOT
 #endif
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
deleted file mode 100644
index 87818a8d3a..0000000000
--- a/board/freescale/t102xqds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1024QDS
-
-config SYS_BOARD
-	default "t102xqds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T102xQDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS
deleted file mode 100644
index 7e30e5f84b..0000000000
--- a/board/freescale/t102xqds/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-T102XQDS BOARD
-#M:	Shengzhou Liu  <Shengzhou.Liu@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/t102xqds/
-F:	include/configs/T102xQDS.h
-F:	configs/T1024QDS_defconfig
-F:	configs/T1024QDS_NAND_defconfig
-F:	configs/T1024QDS_SDCARD_defconfig
-F:	configs/T1024QDS_SPIFLASH_defconfig
-F:	configs/T1024QDS_DDR4_defconfig
-F:	configs/T1024QDS_SECURE_BOOT_defconfig
-F:	configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
deleted file mode 100644
index ae872b46c3..0000000000
--- a/board/freescale/t102xqds/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-else
-obj-y	+= t102xqds.o
-obj-y	+= eth_t102xqds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
-endif
-obj-y   += ddr.o
-obj-y   += law.o
-obj-y   += tlb.o
diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
deleted file mode 100644
index c00e3bafbe..0000000000
--- a/board/freescale/t102xqds/README
+++ /dev/null
@@ -1,328 +0,0 @@
-T1024 SoC Overview
-------------------
-The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
-combines two or one 64-bit Power Architecture e5500 core respectively with high
-performance datapath acceleration logic, and network peripheral bus interfaces
-required for networking and telecommunications. This processor can be used in
-applications such as enterprise WLAN access points, routers, switches, firewall
-and other packet processing intensive small enterprise and branch office appliances,
-and general-purpose embedded computing. Its high level of integration offers
-significant performance benefits and greatly helps to simplify board design.
-
-
-The T1024 SoC includes the following function and features:
-- two e5500 cores, each with a private 256 KB L2 cache
-  - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
-  - Three levels of instructions: User, supervisor, and hypervisor
-  - Independent boot and reset
-  - Secure boot capability
-- 256 KB shared L3 CoreNet platform cache (CPC)
-- Interconnect CoreNet platform
-  - CoreNet coherency manager supporting coherent and noncoherent transactions
-    with prioritization and bandwidth allocation amongst CoreNet endpoints
-  - 150 Gbps coherent read bandwidth
-- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
-- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
-  - Packet parsing, classification, and distribution
-  - Queue management for scheduling, packet sequencing, and congestion management
-  - Cryptography Acceleration (SEC 5.x)
-  - IEEE 1588 support
-  - Hardware buffer management for buffer allocation and deallocation
-  - MACSEC on DPAA-based Ethernet ports
-- Ethernet interfaces
-  - Four 1 Gbps Ethernet controllers
-- Parallel Ethernet interfaces
-  - Two RGMII interfaces
-- High speed peripheral interfaces
-  - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
-  - One SATA controller supporting 1.5 and 3.0 Gb/s operation
-  - One QSGMII interface
-  - Four SGMII interface supporting 1000 Mbps
-  - Three SGMII interfaces supporting up to 2500 Mbps
-  - 10GbE XFI or 10Base-KR interface
-- Additional peripheral interfaces
-  - Two USB 2.0 controllers with integrated PHY
-  - SD/eSDHC/eMMC
-  - eSPI controller
-  - Four I2C controllers
-  - Four UARTs
-  - Four GPIO controllers
-  - Integrated flash controller (IFC)
-  - LCD interface (DIU) with 12 bit dual data rate
-- Multicore programmable interrupt controller (PIC)
-- Two 8-channel DMA engines
-- Single source clocking implementation
-- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-- QUICC Engine block
-  - 32-bit RISC controller for flexible support of the communications peripherals
-  - Serial DMA channel for receive and transmit on all serial channels
-  - Two universal communication controllers, supporting TDM, HDLC, and UART
-
-T1023 Personality
-------------------
-T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
-unavailable deep sleep. Rest of the blocks are almost same as T1024.
-Differences between T1024 and T1023
-Feature		T1024  T1023
-QUICC Engine:	yes    no
-DIU:		yes    no
-Deep Sleep:	yes    no
-I2C controller: 4      3
-DDR:		64-bit 32-bit
-IFC:		32-bit 28-bit
-
-
-T1024QDS board Overview
------------------------
-- SERDES Connections
-  4 lanes supporting the following:
-  - PCI Express: supports Gen 1 and Gen 2
-  - SGMII 1G and SGMII 2.5G
-  - QSGMII
-  - XFI
-  - SATA 2.0
-  - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
-  - Aurora debug with dedicated connectors.
-- DDR Controller
-  - Supports up to 1600 MTPS data-rate.
-  - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
-    - Supports Single-, dual- or quad-rank DIMMs
-  - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
-- IFC/Local Bus
-  - NAND Flash: 8-bit, async, up to 2GB
-  - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
-    - NOR devices support 8 virtual banks
-    - Socketed to allow alternate devices
-  - GASIC: Simple (minimal) target within QIXIS FPGA
-  - PromJET rapid memory download support
-  - IFC Debug/Development card
-- Ethernet
-  - Two on-board RGMII 10M/100M/1G ethernet ports.
-  - One QSGMII interface
-  - Four SGMII interface supporting 1Gbps
-  - Three SGMII interfaces supporting 2.5Gbps
-  - one 10Gbps XFI or 10Base-KR interface
-- QIXIS System Logic FPGA
-  - Manages system power and reset sequencing.
-  - Manages the configurations of DUT, board, and clock for dynamic shmoo.
-  - Collects V-I-T data in background for code/power profiling.
-  - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
-  - General fault monitoring and logging.
-  - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
-- Clocks
-  - System and DDR clock (SYSCLK, DDRCLK).
-    - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
-    - Software programmable in 1 MHz increments from 1-200 MHz.
-  - SERDES clocks
-    - Provides clocks to SerDes blocks and slots.
-    - 100 MHz, 125 MHz and 156.25 MHz options.
-    - Spread-spectrum option for 100 MHz.
-- Power Supplies
-  - Dedicated PMBus regulator for VDD and VDDC.
-  - Adjustable from 0.7V to 1.3V at 35A
-    - VDD can be disabled independanty from VDDC for “deep sleep”.
-    - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
-    - VTT/MVREF automatically track operating voltage.
-    - Dedicated 2.5V VPP supply.
-  - Dedicated regulators/filters for AVDD supplies.
-  - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
-- Video
-  - DIU supports video up to 1280x1024x32 bpp.
-    - Chrontel CH7201 for HDMI connection.
-    - TI DS90C387R for direct LCD connection.
-    - Raw (not encoded) video connector for testing or other encoders.
-- USB
-  - Supports two USB 2.0 ports with integrated PHYs.
-    - Two type A ports with 5V@1.5A per port.
-    - Second port can be converted to OTG mini-AB.
-- SDHC
-  For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
-    - upport for optional clock feedback paths.
-    - Support for optional high-speed voltage translation direction controls.
-    - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
-    - Support for eMMC memory devices.
-- SPI
-  -On-board support of 3 different devices and sizes.
-- Other IO
-  - Two Serial ports
-  - ProfiBus port
-  - Four I2C ports
-
-
-Memory map on T1024QDS
-----------------------
-Start Address  End Address      Description			Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA			4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
-0xF_E000_0000  0xF_E7FF_FFFF    Promjet				128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space		256MB
-0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space		256MB
-0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space		256MB
-0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
-
-
-128MB NOR Flash memory Map
---------------------------
-Start Address   End Address     Definition			Max size
-0xEFF40000      0xEFFFFFFF      U-Boot (current bank)		768KB
-0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)	128KB
-0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)	128KB
-0xEFE00000      0xEFE3FFFF      QE firmware (current bank)	256KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)		44MB
-0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)		7MB + 875KB
-0xEC000000      0xEC01FFFF      RCW (alt bank)			128KB
-0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)		768KB
-0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)		128KB
-0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)		128KB
-0xEBE00000      0xEBE3FFFF      QE firmware (alt bank)		256KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)		44MB
-0xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)	7MB + 875KB
-0xE8000000      0xE801FFFF      RCW (current bank)		128KB
-
-
-SerDes clock vs DIP-switch settings
------------------------------------
-SRDS_PRTCL_S1	SD1_REF_CLK1	SD1_REF_CLK2	SW4[1:4]
-0x6F		100MHz		125MHz		1101
-0xD6		100MHz		100MHz		1111
-0x99		156.25MHz	100MHz		1011
-
-
-T1024 Clock frequency
-----------------------
-BIN   Core     DDR       Platform  FMan
-Bin1: 1400MHz  1600MT/s  400MHz    700MHz
-Bin2: 1200MHz  1600MT/s  400MHz    600MHz
-Bin3: 1000MHz  1600MT/s  400MHz    500MHz
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
-   a. build NOR boot image
-	$  make T1024QDS_defconfig    (For DDR3L, by default)
-	or make T1024QDS_D4_defconfig (For DDR4)
-	$  make
-   b. program u-boot.bin image to NOR flash
-	=> tftp 1000000 u-boot.bin
-	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
-	set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
-   Switching between default bank0 and alternate bank4 on NOR flash
-   To change boot source to vbank4:
-	via software:   run command 'qixis_reset altbank' in U-Boot.
-	via DIP-switch: set SW6[1:4] = '0100'
-
-   To change boot source to vbank0:
-	via software:   run command 'qixis_reset' in U-Boot.
-	via DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
-   a. build PBL image for NAND boot
-	$ make T1024QDS_NAND_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to NAND flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> nand erase 0 $filesize
-	=> nand write 1000000 0 $filesize
-	set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
-   a. build PBL image for SPI boot
-	$ make T1024QDS_SPIFLASH_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SPI flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> sf probe 0
-	=> sf erase 0 f0000
-	=> sf write 1000000 0 $filesize
-	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
-   a. build PBL image for SD boot
-	$ make T1024QDS_SDCARD_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SD/MMC card
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> mmc write 1000000 8 0x800
-	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
-	=> mmc write 1000000 0x820 80
-	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-DIU/QE-TDM/SDXC settings
--------------------
-a) For TDM Riser:     set pin_mux=tdm in hwconfig
-b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
-c) For HDMI(DVI):     set pin_mux=hdmi in hwconfig
-d) For LCD(DFP):      set pin_mux=lcd in hwconfig
-e) For SDXC:	      set adaptor=sdxc in hwconfig
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area		   | Address			|
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB)		|
--------------------------------------------------
-|GD, BD		   | 0xFFFC8000 (4KB)		|
--------------------------------------------------
-|ENV		   | 0xFFFC9000 (8KB)		|
--------------------------------------------------
-|HEAP		   | 0xFFFCB000 (30KB)		|
--------------------------------------------------
-|STACK		   | 0xFFFD8000 (22KB)		|
--------------------------------------------------
-|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
--------------------------------------------------
-
-NAND Flash memory Map on T1024QDS
--------------------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot		1MB
-0x100000	0x15FFFF	U-Boot env	8KB
-0x160000	0x17FFFF	FMAN Ucode	128KB
-0x180000	0x19FFFF	QE Firmware	128KB
-
-
-SD Card memory Map on T1024QDS
-----------------------------------------------------
-Block		#blocks		Definition	Size
-0x008		2048		U-Boot img	1MB
-0x800		0016		U-Boot env	8KB
-0x820		0256		FMAN Ucode	128KB
-0x920		0256		QE Firmware	128KB
-
-
-SPI Flash memory Map on T1024QDS
-----------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot img	1MB
-0x100000	0x101FFF	U-Boot env	8KB
-0x110000	0x12FFFF	FMAN Ucode	128KB
-0x130000	0x14FFFF	QE Firmware	128KB
-
-
-For more details, please refer to T1024QDS Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
deleted file mode 100644
index c27cecd5aa..0000000000
--- a/board/freescale/t102xqds/ddr.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * datarate_mhz_high values need to be in ascending order
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-#if defined(CONFIG_SYS_FSL_DDR4)
-	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
-	{2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
-	{1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			   dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-	struct cpu_type *cpu = gd->arch.cpu;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-	/* Get clk_adjust according to the board ddr freqency and n_banks
-	 * specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found\n");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
-	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
-	debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
-	      pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
-	debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 1;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * rtt and rtt_wr override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
-			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
-#else
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x5f;
-#endif
-
-	/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
-	 * set DDR bus width to 32bit for T1023
-	 */
-	if (cpu->soc_ver == SVR_T1023)
-		popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-
-#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
-	/* for DDR bus 32bit test on T1024 */
-	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
-	void __iomem *qixis_base = (void *)QIXIS_BASE;
-
-	/* does not provide HW signals for power management */
-	clrbits_8(qixis_base + 0x21, 0x2);
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	puts("Initializing....using SPD\n");
-	dram_size = fsl_ddr_sdram();
-#else
-	/* DDR has been initialised by first stage boot loader */
-	dram_size =  fsl_ddr_sdram_size();
-#endif
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
-	fsl_dp_resume();
-#endif
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
deleted file mode 100644
index 49ea21a83a..0000000000
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t102xqds_qixis.h"
-
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT2	3
-#define EMI1_SLOT3	4
-#define EMI1_SLOT4	5
-#define EMI1_SLOT5	6
-#define EMI2		7
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-	"T1024QDS_MDIO_RGMII1",
-	"T1024QDS_MDIO_RGMII2",
-	"T1024QDS_MDIO_SLOT1",
-	"T1024QDS_MDIO_SLOT2",
-	"T1024QDS_MDIO_SLOT3",
-	"T1024QDS_MDIO_SLOT4",
-	"T1024QDS_MDIO_SLOT5",
-	"T1024QDS_MDIO_10GC",
-	"NULL",
-};
-
-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
-static u8 lane_to_slot[] = {2, 3, 4, 5};
-
-static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name;
-
-	if (muxval > EMI2)
-		return NULL;
-
-	name = t1024qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct t1024qds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void t1024qds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-
-	if (muxval < 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-			      int regnum)
-{
-	struct t1024qds_mdio *priv = bus->priv;
-
-	t1024qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-			       int regnum, u16 value)
-{
-	struct t1024qds_mdio *priv = bus->priv;
-
-	t1024qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1024qds_mdio_reset(struct mii_dev *bus)
-{
-	struct t1024qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t1024qds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t1024qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate t1024qds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate t1024qds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t1024qds_mdio_read;
-	bus->write = t1024qds_mdio_write;
-	bus->reset = t1024qds_mdio_reset;
-	strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	struct fixed_link f_link;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
-		if (port == FM1_DTSEC3) {
-			fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
-			fdt_setprop_string(fdt, offset, "phy-connection-type",
-					   "rgmii");
-			fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
-		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		if (port == FM1_DTSEC1) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii_vsc8234_phy_s5");
-		} else if (port == FM1_DTSEC2) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii_vsc8234_phy_s4");
-		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
-		if (port == FM1_DTSEC3) {
-			fdt_set_phy_handle(fdt, compat, addr,
-					   "sgmii_aqr105_phy_s3");
-		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
-		switch (port) {
-		case FM1_DTSEC1:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
-			break;
-		case FM1_DTSEC2:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
-			break;
-		case FM1_DTSEC3:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
-			break;
-		case FM1_DTSEC4:
-			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
-			break;
-		default:
-			break;
-		}
-		fdt_delprop(fdt, offset, "phy-connection-type");
-		fdt_setprop_string(fdt, offset, "phy-connection-type",
-				   "qsgmii");
-		fdt_status_okay_by_alias(fdt, "emi1_slot2");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		/* XFI interface */
-		f_link.phy_id = port;
-		f_link.duplex = 1;
-		f_link.link_speed = 10000;
-		f_link.pause = 0;
-		f_link.asym_pause = 0;
-		/* no PHY for XFI */
-		fdt_delprop(fdt, offset, "phy-handle");
-		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
-		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:D} is configured
- * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	switch (srds_s1) {
-	case 0x46:
-	case 0x47:
-		lane_to_slot[1] = 2;
-		break;
-	default:
-		break;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
-	switch (srds_s1) {
-	case 0xd5:
-	case 0xd6:
-		/* QSGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, 0x8);
-		fm_info_set_phy_address(FM1_DTSEC2, 0x9);
-		fm_info_set_phy_address(FM1_DTSEC3, 0xa);
-		fm_info_set_phy_address(FM1_DTSEC4, 0xb);
-		break;
-	case 0x95:
-	case 0x99:
-		/*
-		 * XFI does not need a PHY to work, but to avoid U-Boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
-		 * MAC, and should not use a real XAUI PHY address, since
-		 * MDIO can access it successfully, and then MDIO thinks the
-		 * XAUI card is used for the XFI MAC, which will cause error.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x6f:
-		/* SGMII in Slot3, Slot4, Slot5 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x7f:
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
-		break;
-	case 0x47:
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x77:
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
-		break;
-	case 0x5a:
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x6a:
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x5b:
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	case 0x6b:
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
-		break;
-	default:
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_SGMII_2500:
-		case PHY_INTERFACE_MODE_QSGMII:
-			if (interface == PHY_INTERFACE_MODE_SGMII) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_FM1_DTSEC1 + idx);
-			} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_2500_FM1_DTSEC1 + idx);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						QSGMII_FM1_A);
-			}
-
-			if (lane < 0)
-				break;
-
-			slot = lane_to_slot[lane];
-			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 4:
-				mdio_mux[i] = EMI1_SLOT4;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 5:
-				mdio_mux[i] = EMI1_SLOT5;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII2;
-			else if (i == FM1_DTSEC4)
-				mdio_mux[i] = EMI1_RGMII1;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		idx = i - FM1_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-						     XFI_FM1_MAC1 + idx);
-			if (lane < 0)
-				break;
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
deleted file mode 100644
index d3c1dba934..0000000000
--- a/board/freescale/t102xqds/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c
deleted file mode 100644
index 1b1cc0483c..0000000000
--- a/board/freescale/t102xqds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
deleted file mode 100644
index 9f4a43ed56..0000000000
--- a/board/freescale/t102xqds/spl.c
+++ /dev/null
@@ -1,156 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/qixis.h"
-#include "t102xqds_qixis.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
-	/*
-	 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
-	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
-	 * This workaround changes RCW source to make all signals enabled.
-	 */
-	u32 porsr1, pinctl;
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK        0xFF800000
-
-	porsr1 = in_be32(&gur->porsr1);
-	pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
-	out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
-
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	ccb_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
-	puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	puts("\nNAND boot...\n");
-#endif
-
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
-	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			       (uchar *)SPL_ENV_ADDR);
-#endif
-
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-
-	i2c_init_all();
-
-	dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/t102xqds/t1024_nand_rcw.cfg b/board/freescale/t102xqds/t1024_nand_rcw.cfg
deleted file mode 100644
index 4b8f7194dc..0000000000
--- a/board/freescale/t102xqds/t1024_nand_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 e8104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
deleted file mode 100644
index 98efca25a2..0000000000
--- a/board/freescale/t102xqds/t1024_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/board/freescale/t102xqds/t1024_sd_rcw.cfg b/board/freescale/t102xqds/t1024_sd_rcw.cfg
deleted file mode 100644
index 3eca275db3..0000000000
--- a/board/freescale/t102xqds/t1024_sd_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 68104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_spi_rcw.cfg b/board/freescale/t102xqds/t1024_spi_rcw.cfg
deleted file mode 100644
index 1601e35fc8..0000000000
--- a/board/freescale/t102xqds/t1024_spi_rcw.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
-# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
-
-# PBL preamble and RCW header for T1024QDS
-aa55aa55 010e0100
-# Serdes protocol 0x6F
-0810000e 00000000 00000000 00000000
-37800001 00000012 58104000 21000000
-00000000 00000000 00000000 00030810
-00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
deleted file mode 100644
index fd489851db..0000000000
--- a/board/freescale/t102xqds/t102xqds.c
+++ /dev/null
@@ -1,499 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "t102xqds.h"
-#include "t102xqds_qixis.h"
-#include "../common/sleep.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *const freq[] = {"100", "125", "156.25", "100.0"};
-	int clock;
-	u8 sw = QIXIS_READ(arch);
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
-	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
-	puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
-	puts("SPI\n");
-#else
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("PromJet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else if (sw == 0x15)
-		printf("IFC Card\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
-	printf("FPGA: v%d (%s), build %d",
-	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
-	       (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	puts("SERDES Reference: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = (sw >> 6) & 3;
-	printf("Clock1=%sMHz ", freq[clock]);
-	clock = (sw >> 4) & 3;
-	printf("Clock2=%sMHz\n", freq[clock]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
-	int ret;
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-
-	ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int board_mux_lane_to_slot(void)
-{
-	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1;
-	u8 brdcfg9;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-
-	brdcfg9 = QIXIS_READ(brdcfg[9]);
-	QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
-
-	switch (srds_prtcl_s1) {
-	case 0:
-		/* SerDes1 is not enabled */
-		break;
-	case 0xd5:
-	case 0x5b:
-	case 0x6b:
-	case 0x77:
-	case 0x6f:
-	case 0x7f:
-		QIXIS_WRITE(brdcfg[12], 0x8c);
-		break;
-	case 0x40:
-		QIXIS_WRITE(brdcfg[12], 0xfc);
-		break;
-	case 0xd6:
-	case 0x5a:
-	case 0x6a:
-	case 0x56:
-		QIXIS_WRITE(brdcfg[12], 0x88);
-		break;
-	case 0x47:
-		QIXIS_WRITE(brdcfg[12], 0xcc);
-		break;
-	case 0x46:
-		QIXIS_WRITE(brdcfg[12], 0xc8);
-		break;
-	case 0x95:
-	case 0x99:
-		brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
-		QIXIS_WRITE(brdcfg[9], brdcfg9);
-		QIXIS_WRITE(brdcfg[12], 0x8c);
-		break;
-	case 0x116:
-		QIXIS_WRITE(brdcfg[12], 0x00);
-		break;
-	case 0x115:
-	case 0x119:
-	case 0x129:
-	case 0x12b:
-		/* Aurora, PCIe, SGMII, SATA */
-		QIXIS_WRITE(brdcfg[12], 0x04);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes Protocol %d\n",
-		       srds_prtcl_s1);
-		return -1;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_ARCH_T1024
-static void board_mux_setup(void)
-{
-	u8 brdcfg15;
-
-	brdcfg15 = QIXIS_READ(brdcfg[15]);
-	brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
-
-	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
-		/* Route QE_TDM multiplexed signals to TDM Riser slot */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
-		QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
-		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
-			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
-	} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
-		/* to UCC (ProfiBus) interface */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
-	} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
-		/* to DVI (HDMI) encoder */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
-	} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
-		/* to DFP (LCD) encoder */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
-			    BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
-	}
-
-	if (hwconfig_arg_cmp("adaptor", "sdxc"))
-		/* Route SPI_CS multiplexed signals to SD slot */
-		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
-			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
-}
-#endif
-
-void board_retimer_ds125df111_init(void)
-{
-	u8 reg;
-
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-	int ret, bus_num = 0;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
-				      1, &dev);
-	if (ret)
-		goto failed;
-
-	/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
-	reg = I2C_MUX_CH7;
-	dm_i2c_write(dev, 0, &reg, 1);
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
-				      1, &dev);
-	if (ret)
-		goto failed;
-
-	reg = I2C_MUX_CH5;
-	dm_i2c_write(dev, 0, &reg, 1);
-
-	/* Access to Control/Shared register */
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
-				      1, &dev);
-	if (ret)
-		goto failed;
-	reg = 0x0;
-	dm_i2c_write(dev, 0xff, &reg, 1);
-
-	/* Read device revision and ID */
-	dm_i2c_read(dev, 1, &reg, 1);
-	debug("Retimer version id = 0x%x\n", reg);
-
-	/* Enable Broadcast */
-	reg = 0x0c;
-	dm_i2c_write(dev, 0xff, &reg, 1);
-
-	/* Reset Channel Registers */
-	dm_i2c_read(dev, 0, &reg, 1);
-	reg |= 0x4;
-	dm_i2c_write(dev, 0, &reg, 1);
-
-	/* Enable override divider select and Enable Override Output Mux */
-	dm_i2c_read(dev, 9, &reg, 1);
-	reg |= 0x24;
-	dm_i2c_write(dev, 9, &reg, 1);
-
-	/* Select VCO Divider to full rate (000) */
-	dm_i2c_read(dev, 0x18, &reg, 1);
-	reg &= 0x8f;
-	dm_i2c_write(dev, 0x18, &reg, 1);
-
-	/* Select active PFD MUX input as re-timed data (001) */
-	dm_i2c_read(dev, 0x1e, &reg, 1);
-	reg &= 0x3f;
-	reg |= 0x20;
-	dm_i2c_write(dev, 0x1e, &reg, 1);
-
-	/* Set data rate as 10.3125 Gbps */
-	reg = 0x0;
-	dm_i2c_write(dev, 0x60, &reg, 1);
-	reg = 0xb2;
-	dm_i2c_write(dev, 0x61, &reg, 1);
-	reg = 0x90;
-	dm_i2c_write(dev, 0x62, &reg, 1);
-	reg = 0xb3;
-	dm_i2c_write(dev, 0x63, &reg, 1);
-	reg = 0xcd;
-	dm_i2c_write(dev, 0x64, &reg, 1);
-	return;
-
-failed:
-	printf("%s: Cannot find udev for a bus %d\n", __func__,
-	       bus_num);
-	return;
-#else
-	/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
-	reg = I2C_MUX_CH7;
-	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
-	reg = I2C_MUX_CH5;
-	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
-
-	/* Access to Control/Shared register */
-	reg = 0x0;
-	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
-
-	/* Read device revision and ID */
-	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
-	debug("Retimer version id = 0x%x\n", reg);
-
-	/* Enable Broadcast */
-	reg = 0x0c;
-	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
-
-	/* Reset Channel Registers */
-	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
-	reg |= 0x4;
-	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
-
-	/* Enable override divider select and Enable Override Output Mux */
-	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
-	reg |= 0x24;
-	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
-
-	/* Select VCO Divider to full rate (000) */
-	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
-	reg &= 0x8f;
-	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
-
-	/* Select active PFD MUX input as re-timed data (001) */
-	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
-	reg &= 0x3f;
-	reg |= 0x20;
-	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
-
-	/* Set data rate as 10.3125 Gbps */
-	reg = 0x0;
-	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
-	reg = 0xb2;
-	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
-	reg = 0x90;
-	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
-	reg = 0xb3;
-	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
-	reg = 0xcd;
-	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
-#endif
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
-	if (is_warm_boot())
-		fsl_dp_disable_console();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2; /* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-	board_mux_lane_to_slot();
-	board_retimer_ds125df111_init();
-
-	/* Increase IO drive strength to address FCS error on RGMII */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_64:
-		return 64000000;
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-#define NUM_SRDS_PLL	2
-int misc_init_r(void)
-{
-#ifdef CONFIG_ARCH_T1024
-	board_mux_setup();
-#endif
-	return 0;
-}
-
-void fdt_fixup_spi_mux(void *blob)
-{
-	int nodeoff = 0;
-
-	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
-		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
-			"eon,en25s64")) >= 0) {
-			fdt_del_node(blob, nodeoff);
-		}
-	} else {
-		/* remove tdm node */
-		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
-			"maxim,ds26522")) >= 0) {
-			fdt_del_node(blob, nodeoff);
-		}
-	}
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-	fdt_fixup_board_enet(blob);
-#endif
-	fdt_fixup_spi_mux(blob);
-
-	return 0;
-}
-
-void qixis_dump_switch(void)
-{
-	int i, nr_of_cfgsw;
-
-	QIXIS_WRITE(cms[0], 0x00);
-	nr_of_cfgsw = QIXIS_READ(cms[1]);
-
-	puts("DIP switch settings dump:\n");
-	for (i = 1; i <= nr_of_cfgsw; i++) {
-		QIXIS_WRITE(cms[0], i);
-		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
-	}
-}
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
deleted file mode 100644
index d327b5edb9..0000000000
--- a/board/freescale/t102xqds/t102xqds.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T102x_QDS_H__
-#define __T102x_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_num);
-
-#endif
diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h
deleted file mode 100644
index b84a33fc48..0000000000
--- a/board/freescale/t102xqds/t102xqds_qixis.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1024QDS_QIXIS_H__
-#define __T1024QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1024/T1023 QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK		0xC0
-#define BRDCFG5_IMX_DIU			0x80
-
-#define BRDCFG5_SPIRTE_MASK		0x07
-#define BRDCFG5_SPIRTE_TDM		0x01
-#define BRDCFG5_SPIRTE_SDHC		0x02
-#define BRDCFG9_XFI_TX_DISABLE		0x10
-
-/* BRDCFG13[0:5] TDM configuration and setup */
-#define BRDCFG13_TDM_MASK		0xfc
-#define BRDCFG13_TDM_INTERFACE		0x37
-#define BRDCFG13_HDLC_LOOPBACK		0x29
-#define BRDCFG13_TDM_LOOPBACK		0x31
-
-/* BRDCFG15[3] controls LCD Panel Powerdown */
-#define BRDCFG15_LCDFM			0x20
-#define BRDCFG15_LCDPD			0x10
-#define BRDCFG15_LCDPD_MASK		0x10
-#define BRDCFG15_LCDPD_ENABLED		0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK		0x03
-#define BRDCFG15_DIUSEL_HDMI		0x00
-#define BRDCFG15_DIUSEL_LCD		0x01
-#define BRDCFG15_DIUSEL_UCC		0x02
-#define BRDCFG15_DIUSEL_TDM		0x03
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66			0x0
-#define QIXIS_SYSCLK_83			0x1
-#define QIXIS_SYSCLK_100		0x2
-#define QIXIS_SYSCLK_125		0x3
-#define QIXIS_SYSCLK_133		0x4
-#define QIXIS_SYSCLK_150		0x5
-#define QIXIS_SYSCLK_160		0x6
-#define QIXIS_SYSCLK_166		0x7
-#define QIXIS_SYSCLK_64			0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66			0x0
-#define QIXIS_DDRCLK_100		0x1
-#define QIXIS_DDRCLK_125		0x2
-#define QIXIS_DDRCLK_133		0x3
-
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
deleted file mode 100644
index 3546331aab..0000000000
--- a/board/freescale/t102xqds/tlb.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
-	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_256K, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
-	/* entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so if needed more, will use entry 16 later.
-	 */
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
deleted file mode 100644
index ec3ff0c1ec..0000000000
--- a/board/freescale/t1040qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1040QDS
-
-config SYS_BOARD
-	default "t1040qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T1040QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS
deleted file mode 100644
index 1e276e3db9..0000000000
--- a/board/freescale/t1040qds/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-T1040QDS BOARD
-M:	Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S:	Maintained
-F:	board/freescale/t1040qds/
-F:	include/configs/T1040QDS.h
-F:	configs/T1040QDS_defconfig
-F:	configs/T1040QDS_DDR4_defconfig
-
-T1040QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/T1040QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
deleted file mode 100644
index e10a54af88..0000000000
--- a/board/freescale/t1040qds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y	+= t1040qds.o
-obj-y	+= ddr.o
-obj-$(CONFIG_PCI)     += pci.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-obj-y	+= eth.o
-obj-y	+= diu.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
deleted file mode 100644
index 6c5ffc07f8..0000000000
--- a/board/freescale/t1040qds/README
+++ /dev/null
@@ -1,169 +0,0 @@
-Overview
---------
-The T1040QDS is a Freescale reference board that hosts the T1040 SoC
-(and variants).
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
-    -  Packet parsing, classification, and distribution
-    -  Queue management for scheduling, packet sequencing, and congestion
-    	management
-    -  Cryptography Acceleration (SEC 5.0)
-    - RegEx Pattern Matching Acceleration (PME 2.2)
-    - IEEE Std 1588 support
-    - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
-    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
-    - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
-   - Four PCI Express 2.0 controllers running at up to 5 GHz
-   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
-   - Upto two QSGMII interface
-   - Upto six SGMII interface supporting 1000 Mbps
-   - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
-   - Two USB 2.0 controllers with integrated PHY
-   - SD/eSDHC/eMMC
-   -  eSPI controller
-   - Four I2C controllers
-   - Four UARTs
-   - Four GPIO controllers
-   - Integrated flash controller (IFC)
-   - LCD and HDMI interface (DIU) with 12 bit dual data rate
-   - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
- T1040QDS board Overview
- -----------------------
- - SERDES Connections, 8 lanes supporting:
-      — PCI Express: supporting Gen 1 and Gen 2;
-      — SGMII
-      — QSGMII
-      — SATA 2.0
-      — Aurora debug with dedicated connectors (T1040 only)
- - DDR Controller
-     - Supports rates of up to 1600 MHz data-rate
-     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- -IFC/Local Bus
-     - NAND flash: 8-bit, async, up to 2GB.
-     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
-     - GASIC: Simple (minimal) target within Qixis FPGA
-     - PromJET rapid memory download support
- - Ethernet
-     - Two on-board RGMII 10/100/1G ethernet ports.
-     - PHY #0 remains powered up during deep-sleep (T1040 only)
- - QIXIS System Logic FPGA
- - Clocks
-     - System and DDR clock (SYSCLK, “DDRCLK”)
-     - SERDES clocks
- - Power Supplies
- - Video
-     - DIU supports video at up to 1280x1024x32bpp
- - USB
-     - Supports two USB 2.0 ports with integrated PHYs
-     — Two type A ports with 5V@1.5A per port.
-     — Second port can be converted to OTG mini-AB
- - SDHC
-     - SDHC port connects directly to an adapter card slot, featuring:
-     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
-     — Supporting eMMC memory devices
- - SPI
-    -  On-board support of 3 different devices and sizes
- - Other IO
-    - Two Serial ports
-    - ProfiBus port
-    - Four I2C ports
-
-Memory map on T1040QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address  End Address      Description                     Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA                      4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
-0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
-0xF_E000_0000  0xF_E7FF_FFFF    Promjet                         128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
-0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
-0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
-0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
-0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
-
-
-NOR Flash memory Map on T1040QDS
---------------------------------
- Start          End             Definition                       Size
-0xEFF40000      0xEFFFFFFF      U-Boot (current bank)            768KB
-0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)        128KB
-0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
-0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
-0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
-0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)                768KB
-0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)            128KB
-0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
-0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
-0xE8000000      0xE801FFFF      RCW (current bank)               128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to T1040QDS
-
-1. U-Boot environment variable hwconfig
-   The default hwconfig is:
-	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
-					dr_mode=host,phy_type=utmi
-   Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
-   fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
-   Commands for switching to alternate bank.
-
-	1. To change from vbank0 to vbank4
-		=> qixis_reset altbank (it will boot using vbank4)
-
-	2.To change from vbank4 to vbank0
-		=> qixis reset (it will boot using vbank0)
-
-T1040 Personality
---------------------
-
-T1022 Personality
---------------------
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality
---------------------
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
deleted file mode 100644
index 0a817d0ee8..0000000000
--- a/board/freescale/t1040qds/ddr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found\n");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 1;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * rtt and rtt_wr override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
-			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x69;
-#else
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
-	void __iomem *qixis_base = (void *)QIXIS_BASE;
-
-	/* does not provide HW signals for power management */
-	clrbits_8(qixis_base + 0x21, 0x2);
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-	puts("Initializing....using SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	puts("    DDR: ");
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
-	fsl_dp_resume();
-#endif
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
deleted file mode 100644
index 0f88698ab5..0000000000
--- a/board/freescale/t1040qds/ddr.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-#ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
-	{1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
-	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
-	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-	{1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
-	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
-	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-#endif
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
deleted file mode 100644
index 0b1aeed69e..0000000000
--- a/board/freescale/t1040qds/diu.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include <fsl_diu_fb.h>
-#include "../common/qixis.h"
-#include "../common/diu_ch7301.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register.  So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-	int ret = 0;
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-
-	/* Program HDMI encoder */
-	/* Switch channel to DIU */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
-
-	/* Set dispaly encoder */
-	ret = diu_set_dvi_encoder(temp);
-	if (ret) {
-		puts("Failed to set DVI encoder\n");
-		return;
-	}
-
-	/* Switch channel to default */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	/* Program pixel clock */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-	/* enable clock*/
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	u32 pixel_format;
-	u8 sw;
-
-	/*Route I2C4 to DIU system as HSYNC/VSYNC*/
-	sw = QIXIS_READ(brdcfg[5]);
-	QIXIS_WRITE(brdcfg[5],
-		    ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
-
-	/*Configure Display ouput port as HDMI*/
-	sw = QIXIS_READ(brdcfg[15]);
-	QIXIS_WRITE(brdcfg[15],
-		    ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
-		      | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	printf("DIU:   Switching to monitor @ %ux%u\n",  xres, yres);
-
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
deleted file mode 100644
index b349b77951..0000000000
--- a/board/freescale/t1040qds/eth.c
+++ /dev/null
@@ -1,592 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY connected to
- * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
- * PHY or by the standard four-port SGMII riser card (VSC).
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-#include "../common/qixis.h"
-
-#include "t1040qds_qixis.h"
-
-#ifdef CONFIG_FMAN_ENET
- /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
- *   Bank 1 -> Lanes A, B, C, D
- *   Bank 2 -> Lanes E, F, G, H
- */
-
- /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
-  * means that the mapping must be determined dynamically, or that the lane
-  * maps to something other than a board slot.
-  */
-static u8 lane_to_slot[] = {
-	0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-static int riser_phy_addr[] = {
-	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII0	0
-#define EMI1_RGMII1	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI1_SLOT6	6
-#define EMI1_SLOT7	7
-#define EMI2		8
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-	"T1040_QDS_MDIO0",
-	"T1040_QDS_MDIO1",
-	"T1040_QDS_MDIO2",
-	"T1040_QDS_MDIO3",
-	"T1040_QDS_MDIO4",
-	"T1040_QDS_MDIO5",
-	"T1040_QDS_MDIO6",
-	"T1040_QDS_MDIO7",
-};
-
-struct t1040_qds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = t1040_qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-static void t1040_qds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if (muxval <= 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	t1040_qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	t1040_qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1040_qds_mdio_reset(struct mii_dev *bus)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t1040_qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate t1040_qds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate t1040_qds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t1040_qds_mdio_read;
-	bus->write = t1040_qds_mdio_write;
-	bus->reset = t1040_qds_mdio_reset;
-	strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-
-	return mdio_register(bus);
-}
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the T1040QDS board the mapping is controlled by ?? register.
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
-		>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	QIXIS_WRITE(cms[0], 0x07);
-
-	switch (serdes1_prtcl) {
-	case 0x60:
-	case 0x66:
-	case 0x67:
-	case 0x69:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		break;
-	case 0x86:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		break;
-	case 0x87:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x89:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[6] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x8d:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0x8F:
-	case 0x85:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xA5:
-		lane_to_slot[1] = 7;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xA7:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		lane_to_slot[7] = 7;
-		break;
-	case 0xAA:
-		lane_to_slot[1] = 7;
-		lane_to_slot[6] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x40:
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		break;
-	default:
-		printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
-		       serdes1_prtcl);
-		break;
-	}
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	phy_interface_t intf = fm_info_get_enet_if(port);
-	char phy[16];
-
-	/* The RGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_RGMII) {
-		sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
-		fdt_set_phy_handle(fdt, compat, addr, phy);
-	}
-
-	/* The SGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_SGMII) {
-		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
-						 + port);
-		u8 slot;
-		if (lane < 0)
-			return;
-		slot = lane_to_slot[lane];
-		if (slot) {
-			/* Slot housing a SGMII riser card */
-			sprintf(phy, "phy_s%x_%02x", slot,
-				(fm_info_get_phy_address(port - FM1_DTSEC1)-
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
-			fdt_set_phy_handle(fdt, compat, addr, phy);
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i, lane, idx;
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-						     SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT3:
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-				break;
-			case EMI1_SLOT5:
-				fdt_status_okay_by_alias(fdt, "emi1_slot5");
-				break;
-			case EMI1_SLOT6:
-				fdt_status_okay_by_alias(fdt, "emi1_slot6");
-				break;
-			case EMI1_SLOT7:
-				fdt_status_okay_by_alias(fdt, "emi1_slot7");
-				break;
-			}
-		break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC4)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
-
-			if (i == FM1_DTSEC5)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
-			break;
-		default:
-			break;
-		}
-	}
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-static void set_brdcfg9_for_gtx_clk(void)
-{
-	u8 brdcfg9;
-	brdcfg9 = QIXIS_READ(brdcfg[9]);
-/* Initializing EPHY2 clock to RGMII mode */
-	brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
-	brdcfg9 |= (BRDCFG9_EPHY2_VAL);
-	QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-void t1040_handle_phy_interface_sgmii(int i)
-{
-	int lane, idx, slot;
-	idx = i - FM1_DTSEC1;
-	lane = serdes_get_first_lane(FSL_SRDS_1,
-			SGMII_FM1_DTSEC1 + idx);
-
-	if (lane < 0)
-		return;
-	slot = lane_to_slot[lane];
-
-	switch (slot) {
-	case 1:
-		mdio_mux[i] = EMI1_SLOT1;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 3:
-		if (FM1_DTSEC4 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[0]);
-		if (FM1_DTSEC5 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[1]);
-
-		mdio_mux[i] = EMI1_SLOT3;
-
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 4:
-		mdio_mux[i] = EMI1_SLOT4;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 5:
-		/* Slot housing a SGMII riser card? */
-		fm_info_set_phy_address(i, riser_phy_addr[0]);
-		mdio_mux[i] = EMI1_SLOT5;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 6:
-		/* Slot housing a SGMII riser card? */
-		fm_info_set_phy_address(i, riser_phy_addr[0]);
-		mdio_mux[i] = EMI1_SLOT6;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 7:
-		if (FM1_DTSEC1 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[0]);
-		if (FM1_DTSEC2 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[1]);
-		if (FM1_DTSEC3 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[2]);
-		if (FM1_DTSEC5 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[3]);
-
-		mdio_mux[i] = EMI1_SLOT7;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	default:
-		break;
-	}
-	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-void t1040_handle_phy_interface_rgmii(int i)
-{
-	fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
-			CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
-			CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
-	mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
-		EMI1_RGMII0;
-	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	unsigned int i;
-#ifdef CONFIG_VSC9953
-	int lane;
-	int phy_addr;
-	phy_interface_t phy_int;
-	struct mii_dev *bus;
-#endif
-
-	printf("Initializing Fman\n");
-	set_brdcfg9_for_gtx_clk();
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-
-	/*
-	 * Program on board RGMII PHY addresses. If the SGMII Riser
-	 * card used, we'll override the PHY address later. For any DTSEC that
-	 * is RGMII, we'll also override its PHY address later. We assume that
-	 * DTSEC4 and DTSEC5 are used for RGMII.
-	 */
-	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_QSGMII:
-			fm_info_set_mdio(i, NULL);
-			break;
-		case PHY_INTERFACE_MODE_SGMII:
-			t1040_handle_phy_interface_sgmii(i);
-			break;
-
-		case PHY_INTERFACE_MODE_RGMII:
-			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
-			t1040_handle_phy_interface_rgmii(i);
-			break;
-		default:
-			break;
-		}
-	}
-
-#ifdef CONFIG_VSC9953
-	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
-		lane = -1;
-		phy_addr = 0;
-		phy_int = PHY_INTERFACE_MODE_NONE;
-		switch (i) {
-		case 0:
-		case 1:
-		case 2:
-		case 3:
-			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
-			/* PHYs connected over QSGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
-						i;
-				phy_int = PHY_INTERFACE_MODE_QSGMII;
-				break;
-			}
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_SW1_MAC1 + i);
-
-			if (lane < 0)
-				break;
-
-			/* PHYs connected over QSGMII */
-			if (i != 3 || lane_to_slot[lane] == 7)
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-					+ i;
-			else
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
-			phy_int = PHY_INTERFACE_MODE_SGMII;
-			break;
-		case 4:
-		case 5:
-		case 6:
-		case 7:
-			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
-			/* PHYs connected over QSGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
-						i - 4;
-				phy_int = PHY_INTERFACE_MODE_QSGMII;
-				break;
-			}
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_SW1_MAC1 + i);
-			/* PHYs connected over SGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-						+ i - 3;
-				phy_int = PHY_INTERFACE_MODE_SGMII;
-			}
-			break;
-		case 8:
-			if (serdes_get_first_lane(FSL_SRDS_1,
-						  SGMII_FM1_DTSEC1) < 0)
-				/* FM1@DTSEC1 is connected to SW1@PORT8 */
-				vsc9953_port_enable(i);
-			break;
-		case 9:
-			if (serdes_get_first_lane(FSL_SRDS_1,
-						  SGMII_FM1_DTSEC2) < 0) {
-				/* Enable L2 On MAC2 using SCFG */
-				struct ccsr_scfg *scfg = (struct ccsr_scfg *)
-						CONFIG_SYS_MPC85xx_SCFG;
-
-				out_be32(&scfg->esgmiiselcr,
-					 in_be32(&scfg->esgmiiselcr) |
-					 (0x80000000));
-				vsc9953_port_enable(i);
-			}
-			break;
-		}
-
-		if (lane >= 0) {
-			bus = mii_dev_for_muxval(lane_to_slot[lane]);
-			vsc9953_port_info_set_mdio(i, bus);
-			vsc9953_port_enable(i);
-		}
-		vsc9953_port_info_set_phy_address(i, phy_addr);
-		vsc9953_port_info_set_phy_int(i, phy_int);
-	}
-
-#endif
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
deleted file mode 100644
index cf27655c14..0000000000
--- a/board/freescale/t1040qds/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
deleted file mode 100644
index 5152cdf18a..0000000000
--- a/board/freescale/t1040qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
deleted file mode 100644
index 121b005baf..0000000000
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cf0 00000000
-09000cf4 fffc0000
-09000cf8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
deleted file mode 100644
index 0d0dfa5a46..0000000000
--- a/board/freescale/t1040qds/t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0a10000c 0c000000 00000000 00000000
-66000002 00000000 fc027000 01000000
-00000000 00000000 00000000 00030810
-00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
deleted file mode 100644
index cf38d843ac..0000000000
--- a/board/freescale/t1040qds/t1040qds.c
+++ /dev/null
@@ -1,307 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/sleep.h"
-#include "../common/qixis.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *const freq[] = {"100", "125", "156.25", "161.13",
-						"122.88", "122.88", "122.88"};
-	int clock;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-	       QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("PromJet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else if (sw == 0x15)
-		printf("IFCCard\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
-	       (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = (sw >> 6) & 3;
-	printf("Clock1=%sMHz ", freq[clock]);
-	clock = (sw >> 4) & 3;
-	printf("Clock2=%sMHz\n", freq[clock]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
-	int ret;
-
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-
-	ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static void qe_board_setup(void)
-{
-	u8 brdcfg15, brdcfg9;
-
-	if (hwconfig("qe") && hwconfig("tdm")) {
-		brdcfg15 = QIXIS_READ(brdcfg[15]);
-		/*
-		 * TDMRiser uses QE-TDM
-		 * Route QE_TDM signals to TDM Riser slot
-		 */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
-	} else if (hwconfig("qe") && hwconfig("uart")) {
-		brdcfg15 = QIXIS_READ(brdcfg[15]);
-		brdcfg9 = QIXIS_READ(brdcfg[9]);
-		/*
-		 * Route QE_TDM signals to UCC
-		 * ProfiBus controlled by UCC3
-		 */
-		brdcfg15 &= 0xfc;
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
-		QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
-	}
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
-	if (is_warm_boot())
-		fsl_dp_disable_console();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_64:
-		return 64000000;
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-#define NUM_SRDS_BANKS	2
-int misc_init_r(void)
-{
-	u8 sw;
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 actual[NUM_SRDS_BANKS] = { 0 };
-	int i;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-		switch (clock) {
-		case 0:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		case 2:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
-			break;
-		}
-	}
-
-	puts("SerDes1");
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 pllcr0 = srds_regs->bank[i].pllcr0;
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
-			       i + 1, serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	qe_board_setup();
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
-
-void qixis_dump_switch(void)
-{
-	int i, nr_of_cfgsw;
-
-	QIXIS_WRITE(cms[0], 0x00);
-	nr_of_cfgsw = QIXIS_READ(cms[1]);
-
-	puts("DIP switch settings dump:\n");
-	for (i = 1; i <= nr_of_cfgsw; i++) {
-		QIXIS_WRITE(cms[0], i);
-		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
-	}
-}
-
-int board_need_mem_reset(void)
-{
-	return 1;
-}
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
deleted file mode 100644
index 781bcdefc9..0000000000
--- a/board/freescale/t1040qds/t1040qds.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T1040_QDS_H__
-#define __T1040_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_bum);
-
-#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
deleted file mode 100644
index 213d7011db..0000000000
--- a/board/freescale/t1040qds/t1040qds_qixis.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1040QDS_QIXIS_H__
-#define __T1040QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1040QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK		0xC0
-#define BRDCFG5_IMX_DIU			0x80
-
-/* BRDCFG9[2] controls EPHY2 Clock */
-#define BRDCFG9_EPHY2_MASK              0x20
-#define BRDCFG9_EPHY2_VAL               0x00
-
-/* BRDCFG15[3] controls LCD Panel Powerdown*/
-#define BRDCFG15_LCDPD_MASK		0x10
-#define BRDCFG15_LCDPD_ENABLED		0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK		0x03
-#define BRDCFG15_DIUSEL_HDMI		0x00
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66			0x0
-#define QIXIS_SYSCLK_83			0x1
-#define QIXIS_SYSCLK_100		0x2
-#define QIXIS_SYSCLK_125		0x3
-#define QIXIS_SYSCLK_133		0x4
-#define QIXIS_SYSCLK_150		0x5
-#define QIXIS_SYSCLK_160		0x6
-#define QIXIS_SYSCLK_166		0x7
-#define QIXIS_SYSCLK_64			0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66			0x0
-#define QIXIS_DDRCLK_100		0x1
-#define QIXIS_DDRCLK_125		0x2
-#define QIXIS_DDRCLK_133		0x3
-
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
deleted file mode 100644
index 216b119135..0000000000
--- a/board/freescale/t1040qds/tlb.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
-	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_256K, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
deleted file mode 100644
index f7c1a0c15d..0000000000
--- a/board/freescale/t4qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T4160QDS || TARGET_T4240QDS
-
-config SYS_BOARD
-	default "t4qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T4240QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
deleted file mode 100644
index 44bb2f5c6d..0000000000
--- a/board/freescale/t4qds/MAINTAINERS
+++ /dev/null
@@ -1,18 +0,0 @@
-T4QDS BOARD
-#M:	Shaohui Xie <Shaohui.Xie@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/t4qds/
-F:	include/configs/T4240QDS.h
-F:	configs/T4160QDS_defconfig
-F:	configs/T4160QDS_NAND_defconfig
-F:	configs/T4160QDS_SDCARD_defconfig
-F:	configs/T4240QDS_defconfig
-F:	configs/T4240QDS_NAND_defconfig
-F:	configs/T4240QDS_SDCARD_defconfig
-F:	configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
-
-T4160QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/T4160QDS_SECURE_BOOT_defconfig
-F:	configs/T4240QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
deleted file mode 100644
index 11144222d3..0000000000
--- a/board/freescale/t4qds/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-else
-obj-$(CONFIG_TARGET_T4160QDS)	+= t4240qds.o eth.o
-obj-$(CONFIG_TARGET_T4240QDS)	+= t4240qds.o eth.o
-obj-$(CONFIG_PCI)	+= pci.o
-endif
-
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README
deleted file mode 100644
index bf238146db..0000000000
--- a/board/freescale/t4qds/README
+++ /dev/null
@@ -1,194 +0,0 @@
-Overview
---------
-The T4240QDS is a high-performance computing evaluation, development and test
-platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
-optimized to support the high-bandwidth DDR3 memory ports, as well as the
-highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
-
-Board Features
-  SERDES Connections
-	32 lanes grouped into four 8-lane banks
-	Two “front side” banks dedicated to Ethernet
-		- High-speed crosspoint switch fabric on selected lanes
-		- Two PCI Express slots with side-band connector supporting
-		- SGMII
-		- XAUI
-		- HiGig
-		- I-pass connectors allow board-to-board and loopback support
-	Two “back side” banks dedicated to other protocols
-		- High-speed crosspoint switch fabric on all lanes
-		- Four PCI Express slots with side-band connector supporting
-		- PCI Express 3.0
-		- SATA 2.0
-		- SRIO 2.0
-		- Supports 4X Aurora debug with two connectors
-  DDR Controllers
-	Three independant 64-bit DDR3 controllers
-	Supports rates of 1866 up to 2133 MHz data-rate
-	Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
-	DDR power supplies 1.5V to all devices with automatic tracking of VTT.
-	Power software-switchable to 1.35V if software detects all DDR3LP devices.
-	MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
-	2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
-	increases by 1 clock.
-
-  IFC/Local Bus
-	NAND flash: 8-bit, async or sync, up to 2GB.
-	NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
-	NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
-		- NOR devices support 16 virtual banks
-	GASIC: Minimal target within Qixis FPGA
-	PromJET rapid memory download support
-	Address demultiplexing handled within FPGA.
-		- Flexible demux allows 8 or 16 bit evaluation.
-	IFC Debug/Development card
-		- Support for 32-bit devices
-  Ethernet
-	Support two on-board RGMII 10/100/1G ethernet ports.
-	SGMII and XAUI support via SERDES block (see above).
-	1588 support via Symmetricom board.
-  QIXIS System Logic FPGA
-	Manages system power and reset sequencing
-	Manages DUT, board, clock, etc. configuration for dynamic shmoo
-	Collects V-I-T data in background for code/power profiling.
-	Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
-	General fault monitoring and logging
-	Runs from ATX “hot” power rails allowing operation while system is off.
-  Clocks
-	System and DDR clock (SYSCLK, “DDRCLK”)
-		- Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
-		- Software selectable in 1MHz increments from 1-200MHz.
-	SERDES clocks
-		- Provides clocks to all SerDes blocks and slots
-		- 100, 125 and 156.25 MHz
-  Power Supplies
-	Dedicated regulators for VDD
-		- Adjustable from (0.7V to 1.3V at 80A
-		- Regulators can be controlled by VID and/or software
-	Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
-		- VTT/MVREF automatically track operating voltage
-	Dedicated regulators/filters for AVDD supplies
-	Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
-  USB
-	Supports two USB 2.0 ports with integrated PHYs
-		- One type A, one type micro-AB with 1.0A power per port.
-  Other IO
-	eSDHC/MMC
-		- SDHC card slot
-	eSPI port
-		- High-speed serial flash
-	Two Serial port
-	Four I2C ports
-  XFI
-	XFI is supported on T4QDS-XFI board which removed slot3 and routed
-	four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
-	direct attach cable(copper), the copper cable is used to emulate
-	10GBASE-KR scenario.
-	So, for XFI usage, there are two scenarios, one will use fiber cable,
-	another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
-	introduced to indicate a XFI port will use copper cable, and U-Boot
-	will fixup the dtb accordingly.
-	It's used as: fsl_10gkr_copper:<10g_mac_name>
-	The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
-	do not have to be coexist in hwconfig. If a MAC is listed in the env
-	"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
-	will be used by default.
-	for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
-	hwconfig, then both four XFI ports will use copper cable.
-	set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
-	XFI ports will use copper cable, the other two XFI ports will use fiber
-	cable.
-
-Memory map
-----------
-The addresses in brackets are physical addresses.
-
-0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff   2GB DDR (more than 2GB is initialized but not mapped under with TLB)
-0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
-0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff  32MB DCSR (includes trace buffers)
-0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff  32MB BMan
-0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff  32MB QMan
-0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
-0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
-0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff  16MB CCSR
-0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff   4KB QIXIS
-0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff   4KB Boot page translation for secondary cores
-
-The physical address of the last (boot page translation) varies with the actual DDR size.
-
-Voltage ID and VDD override
---------------------
-T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
-accordingly. The voltage can also be override by command vdd_override. The
-syntax is
-
-vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
-
-Upon success, the actual voltage will be read back. The value is checked
-for safety and any invalid value will not adjust the voltage.
-
-Another way to override VDD is to use environmental variable, in case of using
-command is too late for some debugging. The syntax is
-
-setenv t4240qds_vdd_mv <voltage in mV>
-saveenv
-reset
-
-The override voltage takes effect when booting.
-
-Note: voltage adjustment needs to be done step by step. Changing voltage too
-rapidly may cause current surge. The voltage stepping is done by software.
-Users can set the final voltage directly.
-
-2-stage NAND/SD boot loader
--------------------------------
-PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
-SPL further initialise DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area		| Address			|
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000	(32KB)		|
--------------------------------------------------
-|GD, BD		| 0xFFFC8000	(4KB)		|
--------------------------------------------------
-|ENV		| 0xFFFC9000	(8KB)		|
--------------------------------------------------
-|HEAP		| 0xFFFCB000	(50KB)		|
--------------------------------------------------
-|STACK		| 0xFFFD8000	(22KB)		|
--------------------------------------------------
-|U-Boot SPL	| 0xFFFD8000 	(160KB)		|
--------------------------------------------------
-
-NAND Flash memory Map on T4QDS
---------------------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot img	1MB
-0x140000	0x15FFFF	U-Boot env      128KB
-0x160000	0x17FFFF	FMAN Ucode      128KB
-
-Micro SD Card memory Map on T4QDS
-----------------------------------------------------
-Block		#blocks		Definition	Size
-0x008		2048		U-Boot img	1MB
-0x800		0016		U-Boot env	8KB
-0x820		0128		FMAN ucode	64KB
-
-Switch Settings: (ON is 1, OFF is 0)
-===============
-NAND boot SW setting:
-SW1[1:8] = 10000010
-SW2[1.1] = 0
-SW6[1:4] = 1001
-
-SD boot SW setting:
-SW1[1:8] = 00100000
-SW2[1.1] = 0
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
deleted file mode 100644
index 4fdd69d424..0000000000
--- a/board/freescale/t4qds/ddr.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	/*
-	 * we use identical timing for all slots. If needed, change the code
-	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
-	 */
-	if (popts->registered_dimm_en)
-		pbsp = rdimms[0];
-	else
-		pbsp = udimms[0];
-
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x63;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-	puts("Initializing....using SPD\n");
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	dram_size = fsl_ddr_sdram();
-#else
-	/* DDR has been initialised by first stage boot loader */
-	dram_size = fsl_ddr_sdram_size();
-#endif
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
deleted file mode 100644
index a28d4314da..0000000000
--- a/board/freescale/t4qds/ddr.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-
-
-#endif
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
deleted file mode 100644
index 810868ff39..0000000000
--- a/board/freescale/t4qds/eth.c
+++ /dev/null
@@ -1,869 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include <linux/libfdt.h>
-
-#include "t4240qds_qixis.h"
-
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII	0
-#define EMI1_SLOT1	1
-#define EMI1_SLOT2	2
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI1_SLOT7	7
-#define EMI2		8
-/* Slot6 and Slot8 do not have EMI connections */
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char *mdio_names[] = {
-	"T4240QDS_MDIO0",
-	"T4240QDS_MDIO1",
-	"T4240QDS_MDIO2",
-	"T4240QDS_MDIO3",
-	"T4240QDS_MDIO4",
-	"T4240QDS_MDIO5",
-	"NULL",
-	"T4240QDS_MDIO7",
-	"T4240QDS_10GC",
-};
-
-static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
-static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
-static u8 slot_qsgmii_phyaddr[5][4] = {
-	{0, 0, 0, 0},/* not used, to make index match slot No. */
-	{0, 1, 2, 3},
-	{4, 5, 6, 7},
-	{8, 9, 0xa, 0xb},
-	{0xc, 0xd, 0xe, 0xf},
-};
-static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
-
-static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = t4240qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct t4240qds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void t4240qds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if ((muxval < 6) || (muxval == 7)) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct t4240qds_mdio *priv = bus->priv;
-
-	t4240qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct t4240qds_mdio *priv = bus->priv;
-
-	t4240qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t4240qds_mdio_reset(struct mii_dev *bus)
-{
-	struct t4240qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t4240qds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t4240qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate T4240QDS MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate T4240QDS private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t4240qds_mdio_read;
-	bus->write = t4240qds_mdio_write;
-	bus->reset = t4240qds_mdio_reset;
-	strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
-				enum fm_port port, int offset)
-{
-	int interface = fm_info_get_enet_if(port);
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
-	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	if (interface == PHY_INTERFACE_MODE_SGMII ||
-	    interface == PHY_INTERFACE_MODE_QSGMII) {
-		switch (port) {
-		case FM1_DTSEC1:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy21");
-			break;
-		case FM1_DTSEC2:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy22");
-			break;
-		case FM1_DTSEC3:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy23");
-			break;
-		case FM1_DTSEC4:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy24");
-			break;
-		case FM1_DTSEC6:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy12");
-			break;
-		case FM1_DTSEC9:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy14");
-			else
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_sgmii4");
-			break;
-		case FM1_DTSEC10:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy13");
-			else
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_sgmii3");
-			break;
-		case FM2_DTSEC1:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy41");
-			break;
-		case FM2_DTSEC2:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy42");
-			break;
-		case FM2_DTSEC3:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy43");
-			break;
-		case FM2_DTSEC4:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy44");
-			break;
-		case FM2_DTSEC6:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy32");
-			break;
-		case FM2_DTSEC9:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy34");
-			else
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_sgmii12");
-			break;
-		case FM2_DTSEC10:
-			if (qsgmiiphy_fix[port])
-				fdt_set_phy_handle(blob, prop, pa,
-						   "sgmii_phy33");
-			else
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_sgmii11");
-			break;
-		default:
-			break;
-		}
-	} else if (interface == PHY_INTERFACE_MODE_XGMII &&
-		  ((prtcl2 == 55) || (prtcl2 == 57))) {
-		/*
-		 * if the 10G is XFI, check hwconfig to see what is the
-		 * media type, there are two types, fiber or copper,
-		 * fix the dtb accordingly.
-		 */
-		int media_type = 0;
-		struct fixed_link f_link;
-		char lane_mode[20] = {"10GBASE-KR"};
-		char buf[32] = "serdes-2,";
-		int off;
-
-		switch (port) {
-		case FM1_10GEC1:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
-				media_type = 1;
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_xfi1");
-				sprintf(buf, "%s%s%s", buf, "lane-a,",
-					(char *)lane_mode);
-			}
-			break;
-		case FM1_10GEC2:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
-				media_type = 1;
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_xfi2");
-				sprintf(buf, "%s%s%s", buf, "lane-b,",
-					(char *)lane_mode);
-			}
-			break;
-		case FM2_10GEC1:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
-				media_type = 1;
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_xfi3");
-				sprintf(buf, "%s%s%s", buf, "lane-d,",
-					(char *)lane_mode);
-			}
-			break;
-		case FM2_10GEC2:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
-				media_type = 1;
-				fdt_set_phy_handle(blob, prop, pa,
-						   "phy_xfi4");
-				sprintf(buf, "%s%s%s", buf, "lane-c,",
-					(char *)lane_mode);
-			}
-			break;
-		default:
-			return;
-		}
-
-		if (!media_type) {
-			/* fixed-link is used for XFI fiber cable */
-			fdt_delprop(blob, offset, "phy-handle");
-			f_link.phy_id = port;
-			f_link.duplex = 1;
-			f_link.link_speed = 10000;
-			f_link.pause = 0;
-			f_link.asym_pause = 0;
-			fdt_setprop(blob, offset, "fixed-link", &f_link,
-				    sizeof(f_link));
-		} else {
-			/* set property for copper cable */
-			off = fdt_node_offset_by_compat_reg(blob,
-					"fsl,fman-memac-mdio", pa + 0x1000);
-			fdt_setprop_string(blob, off, "lane-instance", buf);
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
-	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT1:
-				fdt_status_okay_by_alias(fdt, "emi1_slot1");
-				break;
-			case EMI1_SLOT2:
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-				break;
-			case EMI1_SLOT3:
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-				break;
-			case EMI1_SLOT4:
-				fdt_status_okay_by_alias(fdt, "emi1_slot4");
-				break;
-			default:
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_XGMII:
-			/* check if it's XFI interface for 10g */
-			if ((prtcl2 == 55) || (prtcl2 == 57)) {
-				if (i == FM1_10GEC1 && hwconfig_sub(
-					"fsl_10gkr_copper", "fm1_10g1"))
-					fdt_status_okay_by_alias(
-					fdt, "xfi_pcs_mdio1");
-				if (i == FM1_10GEC2 && hwconfig_sub(
-					"fsl_10gkr_copper", "fm1_10g2"))
-					fdt_status_okay_by_alias(
-					fdt, "xfi_pcs_mdio2");
-				if (i == FM2_10GEC1 && hwconfig_sub(
-					"fsl_10gkr_copper", "fm2_10g1"))
-					fdt_status_okay_by_alias(
-					fdt, "xfi_pcs_mdio3");
-				if (i == FM2_10GEC2 && hwconfig_sub(
-					"fsl_10gkr_copper", "fm2_10g2"))
-					fdt_status_okay_by_alias(
-					fdt, "xfi_pcs_mdio4");
-				break;
-			}
-			switch (i) {
-			case FM1_10GEC1:
-				fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
-				break;
-			case FM1_10GEC2:
-				fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
-				break;
-			case FM2_10GEC1:
-				fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
-				break;
-			case FM2_10GEC2:
-				fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
-				break;
-			default:
-				break;
-			}
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-static void initialize_qsgmiiphy_fix(void)
-{
-	int i;
-	unsigned short reg;
-
-	for (i = 1; i <= 4; i++) {
-		/*
-		 * Try to read if a SGMII card is used, we do it slot by slot.
-		 * if a SGMII PHY address is valid on a slot, then we mark
-		 * all ports on the slot, then fix the PHY address for the
-		 * marked port when doing dtb fixup.
-		 */
-		if (miiphy_read(mdio_names[i],
-				SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
-			debug("Slot%d PHY ID register 2 read failed\n", i);
-			continue;
-		}
-
-		debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
-
-		if (reg == 0xFFFF) {
-			/* No physical device present at this address */
-			continue;
-		}
-
-		switch (i) {
-		case 1:
-			qsgmiiphy_fix[FM1_DTSEC5] = 1;
-			qsgmiiphy_fix[FM1_DTSEC6] = 1;
-			qsgmiiphy_fix[FM1_DTSEC9] = 1;
-			qsgmiiphy_fix[FM1_DTSEC10] = 1;
-			slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
-			slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
-			slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
-			slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
-			break;
-		case 2:
-			qsgmiiphy_fix[FM1_DTSEC1] = 1;
-			qsgmiiphy_fix[FM1_DTSEC2] = 1;
-			qsgmiiphy_fix[FM1_DTSEC3] = 1;
-			qsgmiiphy_fix[FM1_DTSEC4] = 1;
-			slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
-			slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
-			slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
-			slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
-			break;
-		case 3:
-			qsgmiiphy_fix[FM2_DTSEC5] = 1;
-			qsgmiiphy_fix[FM2_DTSEC6] = 1;
-			qsgmiiphy_fix[FM2_DTSEC9] = 1;
-			qsgmiiphy_fix[FM2_DTSEC10] = 1;
-			slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
-			slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
-			slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
-			slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
-			break;
-		case 4:
-			qsgmiiphy_fix[FM2_DTSEC1] = 1;
-			qsgmiiphy_fix[FM2_DTSEC2] = 1;
-			qsgmiiphy_fix[FM2_DTSEC3] = 1;
-			qsgmiiphy_fix[FM2_DTSEC4] = 1;
-			slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
-			slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
-			slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
-			slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-	t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	initialize_qsgmiiphy_fix();
-
-	switch (srds_prtcl_s1) {
-	case 1:
-	case 2:
-	case 4:
-		/* XAUI/HiGig in Slot1 and Slot2 */
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
-		break;
-	case 27:
-	case 28:
-	case 35:
-	case 36:
-		/* SGMII in Slot1 and Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
-		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
-		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
-		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
-		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
-		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-		if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
-			fm_info_set_phy_address(FM1_DTSEC9,
-						slot_qsgmii_phyaddr[1][3]);
-			fm_info_set_phy_address(FM1_DTSEC10,
-						slot_qsgmii_phyaddr[1][2]);
-		}
-		break;
-	case 37:
-	case 38:
-		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
-		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
-		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
-		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
-		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
-		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-		if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
-			fm_info_set_phy_address(FM1_DTSEC9,
-						slot_qsgmii_phyaddr[1][2]);
-			fm_info_set_phy_address(FM1_DTSEC10,
-						slot_qsgmii_phyaddr[1][3]);
-		}
-		break;
-	case 39:
-	case 40:
-	case 45:
-	case 46:
-	case 47:
-	case 48:
-		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
-		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
-		if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
-			fm_info_set_phy_address(FM1_DTSEC10,
-						slot_qsgmii_phyaddr[1][2]);
-			fm_info_set_phy_address(FM1_DTSEC9,
-						slot_qsgmii_phyaddr[1][3]);
-		}
-		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
-		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
-		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
-		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
-		break;
-	default:
-		puts("Invalid SerDes1 protocol for T4240QDS\n");
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			if (interface == PHY_INTERFACE_MODE_QSGMII) {
-				if (idx <= 3)
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-							QSGMII_FM1_A);
-				else
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-							QSGMII_FM1_B);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm1[lane];
-				debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
-				      idx + 1, slot);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						SGMII_FM1_DTSEC1 + idx);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm1[lane];
-				debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-				      idx + 1, slot);
-			}
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			};
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			/* FM1 DTSEC5 routes to RGMII with EC2 */
-			debug("FM1@DTSEC%u is RGMII at address %u\n",
-				idx + 1, 2);
-			if (i == FM1_DTSEC5)
-				fm_info_set_phy_address(i, 2);
-			mdio_mux[i] = EMI1_RGMII;
-			fm_info_set_mdio(i,
-				mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		idx = i - FM1_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
-				/* A fake PHY address to make U-Boot happy */
-				fm_info_set_phy_address(i, i);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						XAUI_FM1_MAC9 + idx);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm1[lane];
-				if (QIXIS_READ(present2) & (1 << (slot - 1)))
-					fm_disable_port(i);
-			}
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
-	switch (srds_prtcl_s2) {
-	case 1:
-	case 2:
-	case 4:
-		/* XAUI/HiGig in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
-		break;
-	case 6:
-	case 7:
-	case 12:
-	case 13:
-	case 14:
-	case 15:
-	case 16:
-	case 21:
-	case 22:
-	case 23:
-	case 24:
-	case 25:
-	case 26:
-		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
-		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		break;
-	case 27:
-	case 28:
-	case 35:
-	case 36:
-		/* SGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
-		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
-		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
-		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
-		break;
-	case 37:
-	case 38:
-		/* QSGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
-		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
-		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
-		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
-		break;
-	case 39:
-	case 40:
-	case 45:
-	case 46:
-	case 47:
-	case 48:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
-		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
-		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
-		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
-		/* QSGMII in Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		break;
-	case 49:
-	case 50:
-	case 51:
-	case 52:
-	case 53:
-	case 54:
-		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		break;
-	case 55:
-	case 57:
-		/* XFI in Slot3, SGMII in Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
-		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
-		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
-		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
-		break;
-	default:
-		puts("Invalid SerDes2 protocol for T4240QDS\n");
-		break;
-	}
-
-	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
-		idx = i - FM2_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-		case PHY_INTERFACE_MODE_QSGMII:
-			if (interface == PHY_INTERFACE_MODE_QSGMII) {
-				if (idx <= 3)
-					lane = serdes_get_first_lane(FSL_SRDS_2,
-							QSGMII_FM2_A);
-				else
-					lane = serdes_get_first_lane(FSL_SRDS_2,
-							QSGMII_FM2_B);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm2[lane];
-				debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
-				      idx + 1, slot);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_2,
-						SGMII_FM2_DTSEC1 + idx);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm2[lane];
-				debug("FM2@DTSEC%u expects SGMII in slot %u\n",
-				      idx + 1, slot);
-			}
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			switch (slot) {
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 4:
-				mdio_mux[i] = EMI1_SLOT4;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			};
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			/*
-			 * If DTSEC5 is RGMII, then it's routed via via EC1 to
-			 * the first on-board RGMII port.  If DTSEC6 is RGMII,
-			 * then it's routed via via EC2 to the second on-board
-			 * RGMII port.
-			 */
-			debug("FM2@DTSEC%u is RGMII at address %u\n",
-				idx + 1, i == FM2_DTSEC5 ? 1 : 2);
-			fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
-			mdio_mux[i] = EMI1_RGMII;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
-		idx = i - FM2_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
-				/* A fake PHY address to make U-Boot happy */
-				fm_info_set_phy_address(i, i);
-			} else {
-				lane = serdes_get_first_lane(FSL_SRDS_2,
-						XAUI_FM2_MAC9 + idx);
-				if (lane < 0)
-					break;
-				slot = lane_to_slot_fsm2[lane];
-				if (QIXIS_READ(present2) & (1 << (slot - 1)))
-					fm_disable_port(i);
-			}
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-#endif /* CONFIG_SYS_NUM_FMAN */
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
deleted file mode 100644
index cb7bdf391b..0000000000
--- a/board/freescale/t4qds/law.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4qds/pci.c b/board/freescale/t4qds/pci.c
deleted file mode 100644
index 26e2a0af4a..0000000000
--- a/board/freescale/t4qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
deleted file mode 100644
index d72d207a76..0000000000
--- a/board/freescale/t4qds/spl.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "t4240qds_qixis.h"
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifdef CONFIG_SPL_NAND_BOOT
-	u32 porsr1, pinctl;
-#endif
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	porsr1 = in_be32(&gur->porsr1);
-	pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
-	out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("" : : : "memory");
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	ccb_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	puts("\nNAND boot...\n");
-#endif
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)SPL_ENV_ADDR);
-#endif
-
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-
-	i2c_init_all();
-
-	dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
deleted file mode 100644
index 8f2032acc7..0000000000
--- a/board/freescale/t4qds/t4240emu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	struct cpu_type *cpu = gd->arch.cpu;
-
-	printf("Board: %sEMU\n", cpu->name);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-	fdt_fixup_liodn(blob);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-	return 0;
-}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
deleted file mode 100644
index 543a2cb6e2..0000000000
--- a/board/freescale/t4qds/t4240qds.c
+++ /dev/null
@@ -1,929 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <linux/delay.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "t4qds.h"
-#include "t4240qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
-				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
-				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
-				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
-				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	unsigned int i;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-	       QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("Promjet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
-	       (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference Clocks: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < MAX_SERDES; i++) {
-		static const char * const freq[] = {
-			"100", "125", "156.25", "161.1328125"};
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-
-		printf("SERDES%u=%sMHz ", i+1, freq[clock]);
-	}
-	puts("\n");
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
-	int ret;
-
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-
-	ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
-#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
-
-static inline int read_voltage(void)
-{
-	int i, ret, voltage_read = 0;
-	u16 vol_mon;
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-	int bus_num = 0;
-#endif
-
-	for (i = 0; i < NUM_READINGS; i++) {
-#ifdef CONFIG_DM_I2C
-		ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
-					      1, &dev);
-		if (ret) {
-			printf("%s: Cannot find udev for a bus %d\n", __func__,
-			       bus_num);
-			return ret;
-		}
-
-		ret = dm_i2c_read(dev,
-				  I2C_VOL_MONITOR_BUS_V_OFFSET,
-				  (void *)&vol_mon, 2);
-#else
-		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
-			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-#endif
-		if (ret) {
-			printf("VID: failed to read core voltage\n");
-			return ret;
-		}
-		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
-			printf("VID: Core voltage sensor error\n");
-			return -1;
-		}
-		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
-		/* LSB = 4mv */
-		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
-		udelay(WAIT_FOR_ADC);
-	}
-	/* calculate the average */
-	voltage_read /= NUM_READINGS;
-
-	return voltage_read;
-}
-
-/*
- * We need to calculate how long before the voltage starts to drop or increase
- * It returns with the loop count. Each loop takes several readings (532us)
- */
-static inline int wait_for_voltage_change(int vdd_last)
-{
-	int timeout, vdd_current;
-
-	vdd_current = read_voltage();
-	/* wait until voltage starts to drop */
-	for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
-		timeout < 100; timeout++) {
-		vdd_current = read_voltage();
-	}
-	if (timeout >= 100) {
-		printf("VID: Voltage adjustment timeout\n");
-		return -1;
-	}
-	return timeout;
-}
-
-/*
- * argument 'wait' is the time we know the voltage difference can be measured
- * this function keeps reading the voltage until it is stable
- */
-static inline int wait_for_voltage_stable(int wait)
-{
-	int timeout, vdd_current, vdd_last;
-
-	vdd_last = read_voltage();
-	udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
-	/* wait until voltage is stable */
-	vdd_current = read_voltage();
-	for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
-		timeout < 100; timeout++) {
-		vdd_last = vdd_current;
-		udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
-		vdd_current = read_voltage();
-	}
-	if (timeout >= 100) {
-		printf("VID: Voltage adjustment timeout\n");
-		return -1;
-	}
-
-	return vdd_current;
-}
-
-static inline int set_voltage(u8 vid)
-{
-	int wait, vdd_last;
-
-	vdd_last = read_voltage();
-	QIXIS_WRITE(brdcfg[6], vid);
-	wait = wait_for_voltage_change(vdd_last);
-	if (wait < 0)
-		return -1;
-	debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
-	wait = wait ? wait : 1;
-
-	vdd_last = wait_for_voltage_stable(wait);
-	if (vdd_last < 0)
-		return -1;
-	debug("VID: Current voltage is %d mV\n", vdd_last);
-
-	return vdd_last;
-}
-
-
-static int adjust_vdd(ulong vdd_override)
-{
-	int re_enable = disable_interrupts();
-	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 fusesr;
-	u8 vid, vid_current;
-	int vdd_target, vdd_current, vdd_last;
-	int ret;
-	unsigned long vdd_string_override;
-	char *vdd_string;
-	static const uint16_t vdd[32] = {
-		0,	/* unused */
-		9875,	/* 0.9875V */
-		9750,
-		9625,
-		9500,
-		9375,
-		9250,
-		9125,
-		9000,
-		8875,
-		8750,
-		8625,
-		8500,
-		8375,
-		8250,
-		8125,
-		10000,	/* 1.0000V */
-		10125,
-		10250,
-		10375,
-		10500,
-		10625,
-		10750,
-		10875,
-		11000,
-		0,	/* reserved */
-	};
-	struct vdd_drive {
-		u8 vid;
-		unsigned voltage;
-	};
-
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
-	if (ret) {
-		debug("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* get the voltage ID from fuse status register */
-	fusesr = in_be32(&gur->dcfg_fusesr);
-	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
-		FSL_CORENET_DCFG_FUSESR_VID_MASK;
-	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
-		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
-			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
-	}
-	vdd_target = vdd[vid];
-
-	/* check override variable for overriding VDD */
-	vdd_string = env_get("t4240qds_vdd_mv");
-	if (vdd_override == 0 && vdd_string &&
-	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
-		vdd_override = vdd_string_override;
-	if (vdd_override >= 819 && vdd_override <= 1212) {
-		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
-		debug("VDD override is %lu\n", vdd_override);
-	} else if (vdd_override != 0) {
-		printf("Invalid value.\n");
-	}
-
-	if (vdd_target == 0) {
-		debug("VID: VID not used\n");
-		ret = 0;
-		goto exit;
-	} else {
-		/* round up and divice by 10 to get a value in mV */
-		vdd_target = DIV_ROUND_UP(vdd_target, 10);
-		debug("VID: vid = %d mV\n", vdd_target);
-	}
-
-	/*
-	 * Check current board VID setting
-	 * Voltage regulator support output to 6.250mv step
-	 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
-	 * the lowest is (vid=0x7f) 0.81875V
-	 */
-	vid_current =  QIXIS_READ(brdcfg[6]);
-	vdd_current = 121250 - (vid_current - 0x40) * 625;
-	debug("VID: Current vid setting is (0x%x) %d mV\n",
-	      vid_current, vdd_current/100);
-
-	/*
-	 * Read voltage monitor to check real voltage.
-	 * Voltage monitor LSB is 4mv.
-	 */
-	vdd_last = read_voltage();
-	if (vdd_last < 0) {
-		printf("VID: Could not read voltage sensor abort VID adjustment\n");
-		ret = -1;
-		goto exit;
-	}
-	debug("VID: Core voltage is at %d mV\n", vdd_last);
-	/*
-	 * Adjust voltage to at or 8mV above target.
-	 * Each step of adjustment is 6.25mV.
-	 * Stepping down too fast may cause over current.
-	 */
-	while (vdd_last > 0 && vid_current < 0x80 &&
-		vdd_last > (vdd_target + 8)) {
-		vid_current++;
-		vdd_last = set_voltage(vid_current);
-	}
-	/*
-	 * Check if we need to step up
-	 * This happens when board voltage switch was set too low
-	 */
-	while (vdd_last > 0 && vid_current >= 0x40 &&
-		vdd_last < vdd_target + 2) {
-		vid_current--;
-		vdd_last = set_voltage(vid_current);
-	}
-	if (vdd_last > 0)
-		printf("VID: Core voltage %d mV\n", vdd_last);
-	else
-		ret = -1;
-
-exit:
-	if (re_enable)
-		enable_interrupts();
-	return ret;
-}
-
-/* Configure Crossbar switches for Front-Side SerDes Ports */
-int config_frontside_crossbar_vsc3316(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
-	int ret;
-
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
-	if (ret)
-		return ret;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	switch (srds_prtcl_s1) {
-	case 37:
-	case 38:
-		/* swap first lane and third lane on slot1 */
-		vsc3316_fsm1_tx[0][1] = 14;
-		vsc3316_fsm1_tx[6][1] = 0;
-		vsc3316_fsm1_rx[1][1] = 2;
-		vsc3316_fsm1_rx[6][1] = 13;
-	case 39:
-	case 40:
-	case 45:
-	case 46:
-	case 47:
-	case 48:
-		/* swap first lane and third lane on slot2 */
-		vsc3316_fsm1_tx[2][1] = 8;
-		vsc3316_fsm1_tx[4][1] = 6;
-		vsc3316_fsm1_rx[2][1] = 10;
-		vsc3316_fsm1_rx[5][1] = 5;
-	default:
-		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
-		if (ret)
-			return ret;
-		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
-		if (ret)
-			return ret;
-		break;
-	}
-
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	switch (srds_prtcl_s2) {
-	case 37:
-	case 38:
-		/* swap first lane and third lane on slot3 */
-		vsc3316_fsm2_tx[2][1] = 11;
-		vsc3316_fsm2_tx[5][1] = 4;
-		vsc3316_fsm2_rx[2][1] = 9;
-		vsc3316_fsm2_rx[4][1] = 7;
-	case 39:
-	case 40:
-	case 45:
-	case 46:
-	case 47:
-	case 48:
-	case 49:
-	case 50:
-	case 51:
-	case 52:
-	case 53:
-	case 54:
-		/* swap first lane and third lane on slot4 */
-		vsc3316_fsm2_tx[6][1] = 3;
-		vsc3316_fsm2_tx[1][1] = 12;
-		vsc3316_fsm2_rx[0][1] = 1;
-		vsc3316_fsm2_rx[6][1] = 15;
-	default:
-		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
-		if (ret)
-			return ret;
-		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
-		if (ret)
-			return ret;
-		break;
-	}
-
-	return 0;
-}
-
-int config_backside_crossbar_mux(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s3, srds_prtcl_s4;
-	u8 brdcfg;
-
-	srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
-	srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
-	switch (srds_prtcl_s3) {
-	case 0:
-		/* SerDes3 is not enabled */
-		break;
-	case 1:
-	case 2:
-	case 9:
-	case 10:
-		/* SD3(0:7) => SLOT5(0:7) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD3MX_MASK;
-		brdcfg |= BRDCFG12_SD3MX_SLOT5;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 3:
-	case 4:
-	case 5:
-	case 6:
-	case 7:
-	case 8:
-	case 11:
-	case 12:
-	case 13:
-	case 14:
-	case 15:
-	case 16:
-	case 17:
-	case 18:
-	case 19:
-	case 20:
-		/* SD3(4:7) => SLOT6(0:3) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD3MX_MASK;
-		brdcfg |= BRDCFG12_SD3MX_SLOT6;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes3 Protocol %d\n",
-		       srds_prtcl_s3);
-		return -1;
-	}
-
-	srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
-	srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
-	switch (srds_prtcl_s4) {
-	case 0:
-		/* SerDes4 is not enabled */
-		break;
-	case 1:
-	case 2:
-		/* 10b, SD4(0:7) => SLOT7(0:7) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_SLOT7;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 3:
-	case 4:
-	case 5:
-	case 6:
-	case 7:
-	case 8:
-		/* x1b, SD4(4:7) => SLOT8(0:3) */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_SLOT8;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	case 9:
-	case 10:
-	case 11:
-	case 12:
-	case 13:
-	case 14:
-	case 15:
-	case 16:
-	case 18:
-		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
-		brdcfg = QIXIS_READ(brdcfg[12]);
-		brdcfg &= ~BRDCFG12_SD4MX_MASK;
-		brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
-		QIXIS_WRITE(brdcfg[12], brdcfg);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes4 Protocol %d\n",
-		       srds_prtcl_s4);
-		return -1;
-	}
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	/* Disable remote I2C connection to qixis fpga */
-	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
-	/*
-	 * Adjust core voltage according to voltage ID
-	 * This function changes I2C mux to channel 2.
-	 */
-	if (adjust_vdd(0))
-		printf("Warning: Adjusting core voltage failed.\n");
-
-	/* Configure board SERDES ports crossbar */
-	config_frontside_crossbar_vsc3316();
-	config_backside_crossbar_mux();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("SYS Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
-	}
-#endif
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("DDR Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
-	}
-#endif
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-int misc_init_r(void)
-{
-	u8 sw;
-	void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	serdes_corenet_t *srds_regs;
-	u32 actual[MAX_SERDES];
-	u32 pllcr0, expected;
-	unsigned int i;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < MAX_SERDES; i++) {
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-		switch (clock) {
-		case 0:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		case 2:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
-			break;
-		case 3:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
-			break;
-		}
-	}
-
-	for (i = 0; i < MAX_SERDES; i++) {
-		srds_regs = srds_base + i * 0x1000;
-		pllcr0 = srds_regs->bank[0].pllcr0;
-		expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
-			       i + 1, serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name>      = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock  : Critical clocks which are not printed already
- * RCW    : RCW source if not printed already
- * Misc   : Other important information not in above catagories
- */
-void board_detail(void)
-{
-	int i;
-	u8 brdcfg[16], dutcfg[16], rst_ctl;
-	int vdd, rcwsrc;
-	static const char * const clk[] = {"66.67", "100", "125", "133.33"};
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	/* Voltage secion */
-	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
-		vdd = read_voltage();
-		if (vdd > 0)
-			printf("Core voltage= %d mV\n", vdd);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-	}
-
-	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
-
-	/* clock section */
-	printf("SYSCLK      = %s MHz\nDDRCLK      = %s MHz\n",
-	       clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
-
-	/* RCW section */
-	rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
-	puts("RCW source  = ");
-	switch (rcwsrc) {
-	case 0x017:
-	case 0x01f:
-		puts("8-bit NOR\n");
-		break;
-	case 0x027:
-	case 0x02F:
-		puts("16-bit NOR\n");
-		break;
-	case 0x040:
-		puts("SDHC/eMMC\n");
-		break;
-	case 0x044:
-		puts("SPI 16-bit addressing\n");
-		break;
-	case 0x045:
-		puts("SPI 24-bit addressing\n");
-		break;
-	case 0x048:
-		puts("I2C normal addressing\n");
-		break;
-	case 0x049:
-		puts("I2C extended addressing\n");
-		break;
-	case 0x108:
-	case 0x109:
-	case 0x10a:
-	case 0x10b:
-		puts("8-bit NAND, 2KB\n");
-		break;
-	default:
-		if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
-			puts("Hard-coded RCW\n");
-		else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
-			puts("8-bit NAND, 4KB\n");
-		else
-			puts("unknown\n");
-		break;
-	}
-
-	/* Misc section */
-	rst_ctl = QIXIS_READ(rst_ctl);
-	puts("HRESET_REQ  = ");
-	switch (rst_ctl & 0x30) {
-	case 0x00:
-		puts("Ignored\n");
-		break;
-	case 0x10:
-		puts("Assert HRESET\n");
-		break;
-	case 0x30:
-		puts("Reset system\n");
-		break;
-	default:
-		puts("N/A\n");
-		break;
-	}
-}
-
-/*
- * Reverse engineering switch settings.
- * Some bits cannot be figured out. They will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
-	int i;
-	u8 sw[9];
-
-	/*
-	 * Any bit with 1 means that bit cannot be reverse engineered.
-	 * It will be displayed as _ in binary format.
-	 */
-	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
-	char buf[10];
-	u8 brdcfg[16], dutcfg[16];
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	sw[0] = dutcfg[0];
-	sw[1] = (dutcfg[1] << 0x07)		|
-		((dutcfg[12] & 0xC0) >> 1)	|
-		((dutcfg[11] & 0xE0) >> 3)	|
-		((dutcfg[6] & 0x80) >> 6)	|
-		((dutcfg[1] & 0x80) >> 7);
-	sw[2] = ((brdcfg[1] & 0x0f) << 4)	|
-		((brdcfg[1] & 0x30) >> 2)	|
-		((brdcfg[1] & 0x40) >> 5)	|
-		((brdcfg[1] & 0x80) >> 7);
-	sw[3] = brdcfg[2];
-	sw[4] = ((dutcfg[2] & 0x01) << 7)	|
-		((dutcfg[2] & 0x06) << 4)	|
-		((~QIXIS_READ(present)) & 0x10)	|
-		((brdcfg[3] & 0x80) >> 4)	|
-		((brdcfg[3] & 0x01) << 2)	|
-		((brdcfg[6] == 0x62) ? 3 :
-		((brdcfg[6] == 0x5a) ? 2 :
-		((brdcfg[6] == 0x5e) ? 1 : 0)));
-	sw[5] = ((brdcfg[0] & 0x0f) << 4)	|
-		((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
-		((brdcfg[0] & 0x40) >> 5);
-	sw[6] = (brdcfg[11] & 0x20)		|
-		((brdcfg[5] & 0x02) << 3);
-	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
-		((brdcfg[5] & 0x10) << 2);
-	sw[8] = ((brdcfg[12] & 0x08) << 4)	|
-		((brdcfg[12] & 0x03) << 5);
-
-	puts("DIP switch (reverse-engineering)\n");
-	for (i = 0; i < 9; i++) {
-		printf("SW%d         = 0b%s (0x%02x)\n",
-		       i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
-	}
-}
-
-static int do_vdd_adjust(struct cmd_tbl *cmdtp,
-			 int flag, int argc,
-			 char *const argv[])
-{
-	ulong override;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-	if (!strict_strtoul(argv[1], 10, &override))
-		adjust_vdd(override);	/* the value is checked by callee */
-	else
-		return CMD_RET_USAGE;
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	vdd_override, 2, 0, do_vdd_adjust,
-	"Override VDD",
-	"- override with the voltage specified in mV, eg. 1050"
-);
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
deleted file mode 100644
index 52e8d5a7be..0000000000
--- a/board/freescale/t4qds/t4240qds_qixis.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T4020QDS_QIXIS_H__
-#define __T4020QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T4020QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66			0x0
-#define QIXIS_SYSCLK_83			0x1
-#define QIXIS_SYSCLK_100		0x2
-#define QIXIS_SYSCLK_125		0x3
-#define QIXIS_SYSCLK_133		0x4
-#define QIXIS_SYSCLK_150		0x5
-#define QIXIS_SYSCLK_160		0x6
-#define QIXIS_SYSCLK_166		0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66			0x0
-#define QIXIS_DDRCLK_100		0x1
-#define QIXIS_DDRCLK_125		0x2
-#define QIXIS_DDRCLK_133		0x3
-
-#define BRDCFG5_IRE			0x20	/* i2c Remote i2c1 enable */
-
-#define BRDCFG12_SD3EN_MASK		0x20
-#define BRDCFG12_SD3MX_MASK		0x08
-#define BRDCFG12_SD3MX_SLOT5		0x08
-#define BRDCFG12_SD3MX_SLOT6		0x00
-#define BRDCFG12_SD4EN_MASK		0x04
-#define BRDCFG12_SD4MX_MASK		0x03
-#define BRDCFG12_SD4MX_SLOT7		0x02
-#define BRDCFG12_SD4MX_SLOT8		0x01
-#define BRDCFG12_SD4MX_AURO_SATA	0x00
-#endif
diff --git a/board/freescale/t4qds/t4_nand_rcw.cfg b/board/freescale/t4qds/t4_nand_rcw.cfg
deleted file mode 100644
index 9386be0faa..0000000000
--- a/board/freescale/t4qds/t4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol  1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 e8020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
deleted file mode 100644
index 8d460039bf..0000000000
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t4qds/t4_sd_rcw.cfg b/board/freescale/t4qds/t4_sd_rcw.cfg
deleted file mode 100644
index 54beb6783d..0000000000
--- a/board/freescale/t4qds/t4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol  1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 68020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
deleted file mode 100644
index 4a8e91b58f..0000000000
--- a/board/freescale/t4qds/t4qds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
deleted file mode 100644
index cd5cf48def..0000000000
--- a/board/freescale/t4qds/tlb.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
-	 * space is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
-	 * fetching ucode and ENV from master
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index 5a998e37d8..440838c112 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -34,7 +34,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* FIXME gpio code here need to handle through DM_GPIO */
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
 	return bus == 0 && cs == 0;
@@ -167,7 +167,7 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifndef CONFIG_DM_SPI
+#if !CONFIG_IS_ENABLED(DM_SPI)
 	vinco_spi0_hw_init();
 #endif
 
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 60a2e3619c..93d1b2febc 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -146,7 +146,7 @@ static void reuse_omap_atags(struct tag_omap *t)
 			}
 			break;
 		case OMAP_TAG_UART:
-			if (!t->u.uart.enabled_uarts)
+			if (t->u.uart.enabled_uarts)
 				serial_was_console_enabled = 1;
 			break;
 		case OMAP_TAG_SERIAL_CONSOLE:
diff --git a/board/novtech/meerkat96/imximage.cfg b/board/novtech/meerkat96/imximage.cfg
index 3bd8cc55e5..86275b84d9 100644
--- a/board/novtech/meerkat96/imximage.cfg
+++ b/board/novtech/meerkat96/imximage.cfg
@@ -25,7 +25,7 @@ BOOT_FROM	sd
 /*
  * Secure boot support
  */
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 0000000000..0cdcd32adc
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+	default "maix"
+
+config SYS_VENDOR
+	default "sipeed"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "sipeed-maix"
+
+config SYS_TEXT_BASE
+	default 0x80000000
+
+config DEFAULT_DEVICE_TREE
+	default "k210-maix-bit"
+
+config NR_CPUS
+	default 2
+
+config NR_DRAM_BANKS
+	default 3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+	select RISCV_PRIV_1_9
+	imply SMP
+	imply DM_SERIAL
+	imply SIFIVE_SERIAL
+	imply SIFIVE_CLINT
+	imply POWER_DOMAIN
+	imply SIMPLE_PM_BUS
+	imply CLK_CCF
+	imply CLK_COMPOSITE_CCF
+	imply CLK_K210
+	imply DM_RESET
+	imply RESET_SYSCON
+	imply SYSRESET
+	imply SYSRESET_SYSCON
+endif
diff --git a/board/sipeed/maix/MAINTAINERS b/board/sipeed/maix/MAINTAINERS
new file mode 100644
index 0000000000..e7bb9ec433
--- /dev/null
+++ b/board/sipeed/maix/MAINTAINERS
@@ -0,0 +1,11 @@
+Sipeed Maix BOARD
+M:	Sean Anderson <seanga2@gmail.com>
+S:	Maintained
+F:	arch/riscv/dts/k210.dtsi
+F:	arch/riscv/dts/k210-maix-bit.dts
+F:	board/sipeed/maix/
+F:	configs/sipeed_maix_bitm_defconfig
+F:	doc/board/sipeed/
+F:	include/configs/sipeed-maix.h
+F:	include/dt-bindings/*/k210-sysctl.h
+F:	test/dm/k210_pll.c
diff --git a/board/sipeed/maix/Makefile b/board/sipeed/maix/Makefile
new file mode 100644
index 0000000000..4acff5b31e
--- /dev/null
+++ b/board/sipeed/maix/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += maix.o
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
new file mode 100644
index 0000000000..cbcb23cf5c
--- /dev/null
+++ b/board/sipeed/maix/maix.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_SDRAM_SIZE;
+}
+
+int board_init(void)
+{
+	int ret, i;
+	const char * const banks[] = { "sram0", "sram1", "airam" };
+	ofnode memory;
+	struct clk clk;
+
+	/* Enable RAM clocks */
+	memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram");
+	if (ofnode_equal(memory, ofnode_null()))
+		return -ENOENT;
+
+	for (i = 0; i < ARRAY_SIZE(banks); i++) {
+		ret = clk_get_by_name_nodev(memory, banks[i], &clk);
+		if (ret)
+			continue;
+
+		ret = clk_enable(&clk);
+		clk_free(&clk);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS
index a3ad2f712a..1e3c0d0ece 100644
--- a/board/tbs/tbs2910/MAINTAINERS
+++ b/board/tbs/tbs2910/MAINTAINERS
@@ -4,4 +4,5 @@ S:	Maintained
 F:	arch/arm/dts/imx6q-tbs2910.dts
 F:	board/tbs/tbs2910/
 F:	configs/tbs2910_defconfig
+F:	doc/board/tbs/
 F:	include/configs/tbs2910.h
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 565f7055cd..e100adfd68 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -3,7 +3,5 @@ M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 F:	board/ti/am335x/
 F:	include/configs/am335x_evm.h
-F:	configs/am335x_boneblack_defconfig
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
-F:	configs/am335x_evm_usbspl_defconfig
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4199bee2e6..123ccaac44 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -912,7 +912,6 @@ struct cpsw_platform_data am335_eth_data = {
 	.slaves			= 2,
 	.slave_data		= slave_data,
 	.ale_entries		= 1024,
-	.bd_ram_ofs		= 0x2000,
 	.mac_control		= 0x20,
 	.active_slave		= 0,
 	.mdio_base		= 0x4a101000,
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 8720eb87a5..511858a5e9 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -61,6 +61,10 @@ static int board_bootmode_has_emmc(void);
 #define board_is_am571x_idk()	board_ti_is("AM571IDK")
 #define board_is_bbai()		board_ti_is("BBONE-AI")
 
+#define board_is_ti_idk()	board_is_am574x_idk() || \
+				board_is_am572x_idk() || \
+				board_is_am571x_idk()
+
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
 #endif
@@ -68,8 +72,7 @@ static int board_bootmode_has_emmc(void);
 DECLARE_GLOBAL_DATA_PTR;
 
 #define GPIO_ETH_LCD		GPIO_TO_PIN(2, 22)
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(7, 11)
 
 /* Touch screen controller to identify the LCD */
 #define OSD_TS_FT_BUS_ADDRESS	0
@@ -667,7 +670,7 @@ void am57x_idk_lcd_detect(void)
 	struct udevice *dev;
 
 	/* Only valid for IDKs */
-	if (board_is_x15() || board_is_am572x_evm() ||  board_is_bbai())
+	if (!board_is_ti_idk())
 		return;
 
 	/* Only AM571x IDK has gpio control detect.. so check that */
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index a22900dcf9..20b75ba133 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -108,10 +108,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 	}
 
 #if defined(CONFIG_TI_SECURE_DEVICE)
-	/* Make HW RNG reserved for secure world use */
-	ret = fdt_disable_node(blob, "/interconnect@100000/trng@4e10000");
+	/* Make Crypto HW reserved for secure world use */
+	ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000");
 	if (ret)
-		printf("%s: disabling TRGN failed %d\n", __func__, ret);
+		printf("%s: disabling SA2UL failed %d\n", __func__, ret);
 #endif
 
 	return 0;
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 429668404a..e09ecda4d7 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -669,17 +669,17 @@ void __maybe_unused set_board_info_env(char *name)
 
 	if (name)
 		env_set("board_name", name);
-	else if (ep->name)
+	else if (strlen(ep->name) != 0)
 		env_set("board_name", ep->name);
 	else
 		env_set("board_name", unknown);
 
-	if (ep->version)
+	if (strlen(ep->version) != 0)
 		env_set("board_rev", ep->version);
 	else
 		env_set("board_rev", unknown);
 
-	if (ep->serial)
+	if (strlen(ep->serial) != 0)
 		env_set("board_serial", ep->serial);
 	else
 		env_set("board_serial", unknown);
@@ -692,22 +692,22 @@ void __maybe_unused set_board_info_env_am6(char *name)
 
 	if (name)
 		env_set("board_name", name);
-	else if (ep->name)
+	else if (strlen(ep->name) != 0)
 		env_set("board_name", ep->name);
 	else
 		env_set("board_name", unknown);
 
-	if (ep->version)
+	if (strlen(ep->version) != 0)
 		env_set("board_rev", ep->version);
 	else
 		env_set("board_rev", unknown);
 
-	if (ep->software_revision)
+	if (strlen(ep->software_revision) != 0)
 		env_set("board_software_revision", ep->software_revision);
 	else
 		env_set("board_software_revision", unknown);
 
-	if (ep->serial)
+	if (strlen(ep->serial) != 0)
 		env_set("board_serial", ep->serial);
 	else
 		env_set("board_serial", unknown);
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index e35f319b46..319bb6aa64 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -12,6 +12,7 @@
 #include <asm/arch/omap.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
+#include <serial.h>
 #include <tca642x.h>
 #include <usb.h>
 #include <linux/delay.h>
@@ -149,39 +150,21 @@ int board_init(void)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
 {
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
 	return 0;
 }
+#endif /* CONFIG_SPL_OS_BOOT */
 
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-static void enable_host_clocks(void)
+int board_eth_init(bd_t *bis)
 {
-	int auxclk;
-	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
-				OPTFCLKEN_HSIC480M_P3_CLK |
-				OPTFCLKEN_HSIC60M_P2_CLK |
-				OPTFCLKEN_HSIC480M_P2_CLK |
-				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
-	/* Enable port 2 and 3 clocks*/
-	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
-	/* Enable port 2 and 3 usb host ports tll clocks*/
-	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
-			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-#ifdef CONFIG_USB_XHCI_OMAP
-	/* Enable the USB OTG Super speed clocks */
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
-			(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
-#endif
-
-	auxclk = readl((*prcm)->scrm_auxclk1);
-	/* Request auxilary clock */
-	auxclk |= AUXCLK_ENABLE_MASK;
-	writel(auxclk, (*prcm)->scrm_auxclk1);
+	return 0;
 }
-#endif
 
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
@@ -223,45 +206,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
-	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	int ret;
-
-	enable_host_clocks();
-
-	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-	if (ret < 0) {
-		puts("Failed to initialize ehci\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-int ehci_hcd_stop(void)
-{
-	return omap_ehci_hcd_stop();
-}
-
-void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
-{
-	/* The LAN9730 needs to be reset after the port power has been set. */
-	if (port == 3) {
-		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
-		udelay(10);
-		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
-	}
-}
-#endif
-
 #ifdef CONFIG_USB_XHCI_OMAP
 /**
  * @brief board_usb_init - Configure EVM board specific configurations
@@ -276,8 +220,6 @@ int board_usb_init(int index, enum usb_init_type init)
 	ret = palmas_enable_ss_ldo();
 #endif
 
-	enable_host_clocks();
-
 	return 0;
 }
 #endif
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 9ebecfdbf5..232d999a29 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -8,6 +8,7 @@
 #include <init.h>
 #include <log.h>
 #include <net.h>
+#include <serial.h>
 #include <asm/mach-types.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
@@ -19,12 +20,6 @@
 
 #include "panda_mux_data.h"
 
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
 #define PANDA_ULPI_PHY_TYPE_GPIO       182
 #define PANDA_BOARD_ID_1_GPIO          101
 #define PANDA_ES_BOARD_ID_1_GPIO        48
@@ -55,6 +50,17 @@ int board_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
 int board_eth_init(bd_t *bis)
 {
 	return 0;
@@ -305,38 +311,6 @@ void board_mmc_power_init(void)
 #endif
 #endif
 
-#ifdef CONFIG_USB_EHCI_HCD
-
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	int ret;
-	unsigned int utmi_clk;
-
-	/* Now we can enable our port clocks */
-	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
-	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
-	setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
-
-	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif
-
 /*
  * get_board_rev() - get board revision
  */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index a5b3504045..5b294ea79b 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -9,6 +9,7 @@
 #include <init.h>
 #include <net.h>
 #include <twl6030.h>
+#include <serial.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
@@ -91,6 +92,17 @@ void board_mmc_power_init(void)
 #endif
 #endif
 
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
 /*
  * get_board_rev() - get board revision
  */
diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
deleted file mode 100644
index 2960099a8e..0000000000
--- a/board/ti/ti814x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI814X_EVM
-
-config SYS_BOARD
-	default "ti814x"
-
-config SYS_VENDOR
-	default "ti"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "ti814x_evm"
-
-endif
diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS
deleted file mode 100644
index b2ee39e8a3..0000000000
--- a/board/ti/ti814x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI814X BOARD
-M:	Tom Rini <trini@konsulko.com>
-S:	Maintained
-F:	board/ti/ti814x/
-F:	include/configs/ti814x_evm.h
-F:	configs/ti814x_evm_defconfig
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
deleted file mode 100644
index c5ff8d0728..0000000000
--- a/board/ti/ti814x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-
-ifdef CONFIG_SPL_BUILD
-obj-y	:= mux.o
-endif
-
-obj-y	+= evm.o
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
deleted file mode 100644
index 8ed80d2f46..0000000000
--- a/board/ti/ti814x/evm.c
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * evm.c
- *
- * Board functions for TI814x EVM
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include "evm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-static const struct cmd_control evm_ddr2_cctrl_data = {
-	.cmd0csratio	= 0x80,
-	.cmd0iclkout	= 0x00,
-
-	.cmd1csratio	= 0x80,
-	.cmd1iclkout	= 0x00,
-
-	.cmd2csratio	= 0x80,
-	.cmd2iclkout	= 0x00,
-};
-
-static const struct emif_regs evm_ddr2_emif0_regs = {
-	.sdram_config			= 0x40801ab2,
-	.ref_ctrl			= 0x10000c30,
-	.sdram_tim1			= 0x0aaaf552,
-	.sdram_tim2			= 0x043631d2,
-	.sdram_tim3			= 0x00000327,
-	.emif_ddr_phy_ctlr_1		= 0x00000007
-};
-
-static const struct emif_regs evm_ddr2_emif1_regs = {
-	.sdram_config			= 0x40801ab2,
-	.ref_ctrl			= 0x10000c30,
-	.sdram_tim1			= 0x0aaaf552,
-	.sdram_tim2			= 0x043631d2,
-	.sdram_tim3			= 0x00000327,
-	.emif_ddr_phy_ctlr_1		= 0x00000007
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
-	.dmm_lisa_map_0			= 0x00000000,
-	.dmm_lisa_map_1			= 0x00000000,
-	.dmm_lisa_map_2			= 0x806c0300,
-	.dmm_lisa_map_3			= 0x806c0300,
-};
-
-static const struct ddr_data evm_ddr2_data = {
-	.datardsratio0		= ((0x35<<10) | (0x35<<0)),
-	.datawdsratio0		= ((0x20<<10) | (0x20<<0)),
-	.datawiratio0		= ((0<<10) | (0<<0)),
-	.datagiratio0		= ((0<<10) | (0<<0)),
-	.datafwsratio0		= ((0x90<<10) | (0x90<<0)),
-	.datawrsratio0		= ((0x50<<10) | (0x50<<0)),
-};
-
-void set_uart_mux_conf(void)
-{
-	/* Set UART pins */
-	enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
-	/* Set MMC pins */
-	enable_mmc1_pin_mux();
-
-	/* Set Ethernet pins */
-	enable_enet_pin_mux();
-}
-
-void sdram_init(void)
-{
-	config_dmm(&evm_lisa_map_regs);
-
-	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
-		   &evm_ddr2_emif0_regs, 0);
-	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
-		   &evm_ddr2_emif1_regs, 1);
-}
-#endif
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-	return 0;
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(1, 0, 0, -1, -1);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x50,
-		.sliver_reg_ofs	= 0x700,
-		.phy_addr	= 1,
-	},
-	{
-		.slave_reg_ofs	= 0x90,
-		.sliver_reg_ofs	= 0x740,
-		.phy_addr	= 0,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x100,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0x600,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x28,
-	.hw_stats_reg_ofs	= 0x400,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_1,
-};
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		printf("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-		else
-			printf("Unable to read MAC address. Set <ethaddr>\n");
-	}
-
-	return cpsw_register(&cpsw_data);
-}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
deleted file mode 100644
index 6aebec62d4..0000000000
--- a/board/ti/ti814x/evm.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _EVM_H
-#define _EVM_H
-
-void enable_uart0_pin_mux(void);
-void enable_mmc1_pin_mux(void);
-void enable_enet_pin_mux(void);
-
-#endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
deleted file mode 100644
index fd9f364511..0000000000
--- a/board/ti/ti814x/mux.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "evm.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(pincntl70), PULLUP_EN | MODE(0x01)},	/* UART0_RXD */
-	{OFFSET(pincntl71), PULLUP_EN | MODE(0x01)},	/* UART0_TXD */
-	{-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
-	{OFFSET(pincntl1), PULLUP_EN | MODE(0x01)},	/* SD1_CLK */
-	{OFFSET(pincntl2), PULLUP_EN | MODE(0x01)},	/* SD1_CMD */
-	{OFFSET(pincntl3), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[0] */
-	{OFFSET(pincntl4), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[1] */
-	{OFFSET(pincntl5), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[2] */
-	{OFFSET(pincntl6), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[3] */
-	{OFFSET(pincntl74), PULLUP_EN | MODE(0x40)},	/* SD1_POW */
-	{OFFSET(pincntl75), MODE(0x40)},		/* SD1_SDWP */
-	{OFFSET(pincntl80), PULLUP_EN | MODE(0x02)},	/* SD1_SDCD */
-	{-1},
-};
-
-static struct module_pin_mux enet_pin_mux[] = {
-	{OFFSET(pincntl232), MODE(0x01)},		/* EMAC_RMREFCLK */
-	{OFFSET(pincntl233), PULLUP_EN | MODE(0x01)},	/* MDCLK */
-	{OFFSET(pincntl234), PULLUP_EN | MODE(0x01)},	/* MDIO */
-	{OFFSET(pincntl235), MODE(0x01)},		/* EMAC[0]_MTCLK */
-	{OFFSET(pincntl236), MODE(0x01)},		/* EMAC[0]_MCOL */
-	{OFFSET(pincntl237), MODE(0x01)},		/* EMAC[0]_MCRS */
-	{OFFSET(pincntl238), MODE(0x01)},		/* EMAC[0]_MRXER */
-	{OFFSET(pincntl239), MODE(0x01)},		/* EMAC[0]_MRCLK */
-	{OFFSET(pincntl240), MODE(0x01)},		/* EMAC[0]_MRXD[0] */
-	{OFFSET(pincntl241), MODE(0x01)},		/* EMAC[0]_MRXD[1] */
-	{OFFSET(pincntl242), MODE(0x01)},		/* EMAC[0]_MRXD[2] */
-	{OFFSET(pincntl243), MODE(0x01)},		/* EMAC[0]_MRXD[3] */
-	{OFFSET(pincntl244), MODE(0x01)},		/* EMAC[0]_MRXD[4] */
-	{OFFSET(pincntl245), MODE(0x01)},		/* EMAC[0]_MRXD[5] */
-	{OFFSET(pincntl246), MODE(0x01)},		/* EMAC[0]_MRXD[6] */
-	{OFFSET(pincntl247), MODE(0x01)},		/* EMAC[0]_MRXD[7] */
-	{OFFSET(pincntl248), MODE(0x01)},		/* EMAC[0]_MRXDV */
-	{OFFSET(pincntl249), MODE(0x01)},		/* EMAC[0]_GMTCLK */
-	{OFFSET(pincntl250), MODE(0x01)},		/* EMAC[0]_MTXD[0] */
-	{OFFSET(pincntl251), MODE(0x01)},		/* EMAC[0]_MTXD[1] */
-	{OFFSET(pincntl252), MODE(0x01)},		/* EMAC[0]_MTXD[2] */
-	{OFFSET(pincntl253), MODE(0x01)},		/* EMAC[0]_MTXD[3] */
-	{OFFSET(pincntl254), MODE(0x01)},		/* EMAC[0]_MTXD[4] */
-	{OFFSET(pincntl255), MODE(0x01)},		/* EMAC[0]_MTXD[5] */
-	{OFFSET(pincntl256), MODE(0x01)},		/* EMAC[0]_MTXD[6] */
-	{OFFSET(pincntl257), MODE(0x01)},		/* EMAC[0]_MTXD[7] */
-	{OFFSET(pincntl258), MODE(0x01)},		/* EMAC[0]_MTXEN */
-};
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_mmc1_pin_mux(void)
-{
-	configure_module_pin_mux(mmc1_pin_mux);
-}
-
-void enable_enet_pin_mux(void)
-{
-	configure_module_pin_mux(enet_pin_mux);
-}
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
index 360beaef8e..e7cc2c2dec 100644
--- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
 	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
 	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
-	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100800U),
 	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
 	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
 	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
index ae4666f7d5..0f141260ff 100644
--- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
 	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U),
 	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
-	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100800U),
 	EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
 	EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
 	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 18b3d3f542..4c21731eed 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -3,7 +3,7 @@
  * Toradex Colibri PXA270 Support
  *
  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
  */
 
 #include <common.h>
@@ -17,6 +17,7 @@
 #include <asm/arch/regs-uart.h>
 #include <asm/io.h>
 #include <dm/platdata.h>
+#include <dm/platform_data/pxa_mmc_gen.h>
 #include <dm/platform_data/serial_pxa.h>
 #include <netdev.h>
 #include <serial.h>
@@ -36,7 +37,7 @@ int board_init(void)
 	/* arch number of Toradex Colibri PXA270 */
 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
 
-	/* adress of boot parameters */
+	/* address of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
 
 	return 0;
@@ -86,7 +87,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
 
 	/* Set port power control mask bits, only 3 ports. */
-	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+	writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB);
 
 	/* enable port 2 */
 	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
@@ -110,8 +111,6 @@ void usb_board_stop(void)
 	udelay(10);
 
 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
-	return;
 }
 #endif
 
@@ -123,11 +122,22 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #ifdef	CONFIG_CMD_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	pxa_mmc_register(0);
 	return 0;
 }
+#else /* !CONFIG_IS_ENABLED(DM_MMC) */
+static const struct pxa_mmc_plat mmc_platdata = {
+	.base = (struct pxa_mmc_regs *)MMC0_BASE,
+};
+
+U_BOOT_DEVICE(pxa_mmcs) = {
+	.name = "pxa_mmc",
+	.platdata = &mmc_platdata,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
 #endif
 
 static const struct pxa_serial_platdata serial_platdata = {
diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 0c46de7599..73e2b0eac7 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -399,7 +399,8 @@ static int zynq_verify_image(u32 src_ptr)
 			status = zynq_decrypt_load(part_load_addr,
 						   part_img_len,
 						   part_dst_addr,
-						   part_data_len);
+						   part_data_len,
+						   BIT_NONE);
 			if (status != 0) {
 				printf("DECRYPTION_FAIL\n");
 				return -1;
@@ -438,22 +439,42 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc,
 	char *endp;
 	u32 srcaddr, srclen, dstaddr, dstlen;
 	int status;
+	u8 imgtype = BIT_NONE;
 
 	if (argc < 5 && argc > cmdtp->maxargs)
 		return CMD_RET_USAGE;
 
-	srcaddr = simple_strtoul(argv[2], &endp, 16);
-	if (*argv[2] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	srclen = simple_strtoul(argv[3], &endp, 16);
-	if (*argv[3] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	dstaddr = simple_strtoul(argv[4], &endp, 16);
-	if (*argv[4] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
-	dstlen = simple_strtoul(argv[5], &endp, 16);
-	if (*argv[5] == 0 || *endp != 0)
-		return CMD_RET_USAGE;
+	if (argc == 5) {
+		if (!strcmp("load", argv[2]))
+			imgtype = BIT_FULL;
+		else if (!strcmp("loadp", argv[2]))
+			imgtype = BIT_PARTIAL;
+		else
+			return CMD_RET_USAGE;
+
+		srcaddr = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+
+		dstaddr = 0xFFFFFFFF;
+		dstlen = srclen;
+	} else {
+		srcaddr = simple_strtoul(argv[2], &endp, 16);
+		if (*argv[2] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstaddr = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstlen = simple_strtoul(argv[5], &endp, 16);
+		if (*argv[5] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+	}
 
 	/*
 	 * Roundup source and destination lengths to
@@ -464,7 +485,8 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (dstlen % 4)
 		dstlen = roundup(dstlen, 4);
 
-	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2);
+	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+				   dstlen >> 2, imgtype);
 	if (status != 0)
 		return CMD_RET_FAILURE;
 
@@ -517,6 +539,10 @@ static char zynq_help_text[] =
 	"                - Decrypts the encrypted image present in source\n"
 	"                  address and places the decrypted image at\n"
 	"                  destination address\n"
+	"aes load <srcaddr> <srclen>\n"
+	"aes loadp <srcaddr> <srclen>\n"
+	"       if operation type is load or loadp, it loads the encrypted\n"
+	"       full or partial bitstream on to PL respectively.\n"
 #endif
 	;
 #endif
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index 0f1f26986f..c0d28a73e4 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -130,8 +130,27 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 #endif
 
+static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	u32 addr, size;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 16);
+	flush_dcache_range((ulong)addr, (ulong)(addr + size));
+
+	zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr,
+					(size_t)size);
+
+	return 0;
+}
+
 static struct cmd_tbl cmd_zynqmp_sub[] = {
 	U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
+	U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
 	U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""),
 	U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""),
 #ifdef CONFIG_DEFINE_TCM_OCM_MMAP
@@ -184,6 +203,7 @@ static char zynqmp_help_text[] =
 	"		       to be initialized. Supported modes will be\n"
 	"		       lock(0)/split(1)\n"
 #endif
+	"zynqmp pmufw address size - load PMU FW configuration object\n"
 	;
 #endif
 
diff --git a/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
new file mode 100644
index 0000000000..dbed7b789e
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
@@ -0,0 +1,1038 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU);
+	psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU);
+	psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U);
+	psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+	psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+	int count = 0;
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+static void psu_init_sdio_pinmux(void)
+{
+	if (Xil_In32(0xFF0A0064U) & (1U << 19)) {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+
+		psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U);
+
+		psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U);
+	} else {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	}
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	psu_init_sdio_pinmux();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index cb72914adb..ebb7172908 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -354,11 +354,14 @@ static int multi_boot(void)
 
 	multiboot = readl(&csu_base->multi_boot);
 
-	printf("Multiboot:\t%x\n", multiboot);
+	printf("Multiboot:\t%d\n", multiboot);
 
 	return 0;
 }
 
+#define PS_SYSMON_ANALOG_BUS_VAL	0x3210
+#define PS_SYSMON_ANALOG_BUS_REG	0xFFA50914
+
 int board_init(void)
 {
 #if defined(CONFIG_ZYNQMP_FIRMWARE)
@@ -378,6 +381,9 @@ int board_init(void)
 
 	printf("EL Level:\tEL%d\n", current_el());
 
+	/* Bug in ROM sets wrong value in this register */
+	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
+
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
     defined(CONFIG_SPL_BUILD))