Merge tag 'rel_imx_5.4.70_2.3.6' into toradex_imx_v2020.04_5.4.70_2.3.0

"rel_imx_5.4.70_2.3.6"

3 files changed, 93 insertions, 1 deletions

diff --git a/board/freescale/imx8mm_ab2/imx8mm_ab2.c b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
index 4483a8a81d..544211bec9 100644
--- a/board/freescale/imx8mm_ab2/imx8mm_ab2.c
+++ b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
@@ -25,6 +25,8 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <spl.h>
+#include <usb.h>
+#include "../common/tcpc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,12 +123,84 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /* i2c2*/
+	.addr = 0x1d,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n", __func__, ret);
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	imx8m_usb_power(index, true);
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(&port1);
+	else
+		tcpc_setup_ufp_mode(&port1);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (init == USB_INIT_HOST)
+		ret = tcpc_disable_src_vbus(&port1);
+
+	imx8m_usb_power(index, false);
+
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	int ret = 0;
+
+	tcpc_setup_ufp_mode(&port1);
+	ret = tcpc_get_cc_status(&port1, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_DM_REGULATOR
 	regulators_enable_boot_on(false);
 #endif
 
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
 #ifdef CONFIG_FEC_MXC
 	setup_fec();
 #endif
diff --git a/board/freescale/imx8mm_ab2/spl.c b/board/freescale/imx8mm_ab2/spl.c
index 8dd03906a6..e1dd434242 100644
--- a/board/freescale/imx8mm_ab2/spl.c
+++ b/board/freescale/imx8mm_ab2/spl.c
@@ -51,7 +51,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 	case NAND_BOOT:
 		return BOOT_DEVICE_NAND;
 	case USB_BOOT:
-		return BOOT_DEVICE_NONE;
+		return BOOT_DEVICE_BOARD;
 	default:
 		return BOOT_DEVICE_NONE;
 	}
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index bb8211dd7c..120810a111 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -218,6 +218,21 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+#define GPR_PCIE_VREG_BYPASS	BIT(12)
+static void enable_pcie_vreg(bool enable)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	if (!enable) {
+		setbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS);
+		setbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS);
+	} else {
+		clrbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS);
+		clrbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS);
+	}
+}
+
 void board_init_f(ulong dummy)
 {
 	int ret;
@@ -225,6 +240,9 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	/* PCIE_VPH connects to 3.3v on EVK, enable VREG to generate 1.8V to PHY */
+	enable_pcie_vreg(true);
+
 	arch_cpu_init();
 
 	init_uart_clk(0);