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authorTom Rini <trini@konsulko.com>2016-07-21 18:54:58 -0400
committerTom Rini <trini@konsulko.com>2016-07-21 18:54:58 -0400
commit9f84da8de1873593d9b708aa4a8a24f46e67c744 (patch)
treeb1c27779a2aa36c02dc2ae507fcd3e9354658fb1 /board
parent95d52733036af7438a5285d729d53844ec48c63e (diff)
parent2a5f7f20747637cd1f94d4accfd7caa99a7c6035 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Diffstat (limited to 'board')
-rw-r--r--board/nvidia/p2371-2180/p2371-2180.c22
-rw-r--r--board/nvidia/p2571/max77620_init.h2
2 files changed, 24 insertions, 0 deletions
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 0f587eaaa79..dbdc1b65e68 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -30,6 +30,28 @@ void pin_mux_mmc(void)
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+ /* Disable LDO4 discharge */
+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret) {
+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+ } else {
+ val &= ~BIT(1); /* ADE */
+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+ }
+
+ /* Set MBLPD */
+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret) {
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ } else {
+ val |= BIT(6); /* MBLPD */
+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ }
}
/*
diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h
index 92c3719112a..39e550149aa 100644
--- a/board/nvidia/p2571/max77620_init.h
+++ b/board/nvidia/p2571/max77620_init.h
@@ -13,6 +13,8 @@
#define MAX77620_I2C_ADDR 0x78
#define MAX77620_I2C_ADDR_7BIT 0x3C
+#define MAX77620_CNFGGLBL1_REG 0x00
+
#define MAX77620_SD0_REG 0x16
#define MAX77620_SD1_REG 0x17
#define MAX77620_SD2_REG 0x18