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authorYe Li <ye.li@nxp.com>2017-12-13 00:22:09 -0600
committerYe Li <ye.li@nxp.com>2018-04-27 02:30:55 -0700
commit3c8d8b0a95f8b1132e301e7e00955846b12aa4cc (patch)
treec6c44dca553872ccfd7bc0ef1168eb6a34e82e4a /board
parent380791dc105256494d30fc1883978808cf83fc04 (diff)
MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source
Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 242823400c5bd59960e1b40d941e177e8ebad57e)
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx7ulp_evk/imximage.cfg2
-rw-r--r--board/freescale/mx7ulp_evk/plugin.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index a5c8c4ed1c..ab7c8fe759 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -46,7 +46,7 @@ DATA 4 0x403f00dc 0x00000000
DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
-DATA 4 0x403e0508 0x00160000
+DATA 4 0x403e0508 0x00160002
DATA 4 0x403E0510 0x00000002
DATA 4 0x403E0514 0x00000005
DATA 4 0x403e0500 0x00000001
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index 81ebcc5019..51beaf94d7 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -19,7 +19,7 @@
ldr r3, =0x80808080
str r3, [r2, #0x50c]
- ldr r3, =0x00160000
+ ldr r3, =0x00160002
str r3, [r2, #0x508]
ldr r3, =0x00000002
str r3, [r2, #0x510]