diff options
author | Philippe Schenker <philippe.schenker@toradex.com> | 2019-09-10 17:37:59 +0200 |
---|---|---|
committer | Max Krummenacher <max.krummenacher@toradex.com> | 2020-03-05 19:22:21 +0100 |
commit | 1a2549a3e2ba7a44f9e85330ae54f4290e99f7b9 (patch) | |
tree | 2710a98549af96861cdae1693adbf258f9489142 /board | |
parent | 413e785e9d6754cb423908af11744842d6345cdb (diff) |
apalis-imx8qxp: initial add
Initial board support for Apalis iMX8QXP using a copy of Colibri iMX8QXP.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/toradex/apalis-imx8qxp/Kconfig | 38 | ||||
-rw-r--r-- | board/toradex/apalis-imx8qxp/Makefile | 6 | ||||
-rw-r--r-- | board/toradex/apalis-imx8qxp/apalis-imx8qxp.c | 447 |
3 files changed, 491 insertions, 0 deletions
diff --git a/board/toradex/apalis-imx8qxp/Kconfig b/board/toradex/apalis-imx8qxp/Kconfig new file mode 100644 index 0000000000..f89df49864 --- /dev/null +++ b/board/toradex/apalis-imx8qxp/Kconfig @@ -0,0 +1,38 @@ +if TARGET_APALIS_IMX8QXP + +config SYS_BOARD + default "apalis-imx8qxp" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis-imx8qxp" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CMD_IMX_MFGR + bool "Enable factory testing commands for Toradex Apalis iMX8QXP modules" + help + This adds the commands + pf8100_otp_prog - Program the OTP fuses on the PMIC PF8100 + If executed on already fused modules it doesn't change any fuse setting. + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis-imx8qxp/Makefile b/board/toradex/apalis-imx8qxp/Makefile new file mode 100644 index 0000000000..e59b206da9 --- /dev/null +++ b/board/toradex/apalis-imx8qxp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2018-2019 Toradex +# + +obj-y += apalis-imx8qxp.o diff --git a/board/toradex/apalis-imx8qxp/apalis-imx8qxp.c b/board/toradex/apalis-imx8qxp/apalis-imx8qxp.c new file mode 100644 index 0000000000..ddc34054b6 --- /dev/null +++ b/board/toradex/apalis-imx8qxp/apalis-imx8qxp.c @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 Toradex + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <i2c.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <dm.h> +#include <imx8_hsio.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/video.h> +#include <asm/arch/video_common.h> +#include <power-domain.h> +#include <asm/arch/lpcg.h> + +#include "../common/tdx-cfg-block.h" + +#ifdef CONFIG_TDX_CMD_IMX_MFGR +unsigned pmic_init(void); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_pm_clock_rate_t rate; + sc_err_t sciErr = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* This works around that having only UART1 up the baudrate is 1.2M + * instead of 115.2k. Set UART0 clock root to 80 MHz */ + rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Power up UART1 */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_1, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART1 clock root to 80 MHz */ + rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_1, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART1 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_1, SC_PM_CLK_PER, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_CD_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void board_mem_get_layout(uint64_t *phys_sdram_1_start, + uint64_t *phys_sdram_1_size, + uint64_t *phys_sdram_2_start, + uint64_t *phys_sdram_2_size) +{ + sc_ipc_t ipc = gd->arch.ipc_channel_handle; + uint32_t is_dualx = 0, val = 0; + sc_err_t sciErr = sc_misc_otp_fuse_read(ipc, 6, &val); + + if (sciErr == SC_ERR_NONE) { + /* DX has two A35 cores disabled */ + is_dualx = (val & 0xf) != 0x0; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + if (is_dualx) + /* Our DX based SKUs only have 1 GB RAM */ + *phys_sdram_1_size = SZ_1G; + else + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + if (!power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + if (!power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_FEC_MXC +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + /* Todo: Does this work for KSZ9131 ? */ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#undef CONFIG_MXC_GPIO /* TODO */ +#ifdef CONFIG_MXC_GPIO +#define IOEXP_RESET IMX_GPIO_NR(1, 1) + +static iomux_cfg_t board_gpios[] = { + SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("gpio@1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); + + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: Apalis iMX8X ########## need to move to common handling\n"); + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) + printf("\nSCI error! Invalid handle\n"); + +#ifdef SCI_FORCE_ABORT + sc_rpc_msg_t abort_msg; + + puts("Send abort request\n"); + RPC_SIZE(&abort_msg) = 1; + RPC_SVC(&abort_msg) = SC_RPC_SVC_ABORT; + sc_ipc_write(SC_IPC_CH, &abort_msg); + + /* Close IPC channel */ + sc_ipc_close(SC_IPC_CH); +#endif /* SCI_FORCE_ABORT */ + + return 0; +} + +/* Only Enable USB3 resources currently */ +int board_usb_init(int index, enum usb_init_type init) +{ +#ifndef CONFIG_DM_USB + struct power_domain pd; + int ret; + + /* Power on usb */ + if (!power_domain_lookup_name("conn_usb2", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2 Power up failed! (error = %d)\n", ret); + } + + if (!power_domain_lookup_name("conn_usb2_phy", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("conn_usb2_phy Power up failed! (error = %d)\n", ret); + } +#endif + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart1", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif +void board_late_mmc_env_init() {} +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Apalis iMX8QXP"); + env_set("board_rev", "v1.0"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ +#ifdef TODO + struct gpio_desc desc; + int ret; + + /* MIPI_DSI0_EN on IOEXP 0x1a port 6, MIPI_DSI1_EN on IOEXP 0x1d port 7 */ + ret = dm_gpio_lookup_name("gpio@1a_6", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lvds0_en"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(13); +#endif +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* LVDS0 */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ |