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authorPriyanka Jain <priyanka.jain@nxp.com>2020-09-21 15:36:25 +0530
committerTom Rini <trini@konsulko.com>2020-09-24 08:27:44 -0400
commit6d1dd76afe85947d605923dd7fc9f4ca7cf8c72d (patch)
treeed61f718be1e1caed9f8714299f7e673a898de97 /board
parent53e3096cd0a76c59c69250dd46e8278dc1db553b (diff)
board/freescale: Remove P1021RDB board support
Remove NXP powerpc P1021RDB board support as it is no longer maintained. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/p1_p2_rdb_pc/Kconfig1
-rw-r--r--board/freescale/p1_p2_rdb_pc/MAINTAINERS8
-rw-r--r--board/freescale/p1_p2_rdb_pc/ddr.c3
-rw-r--r--board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c77
4 files changed, 1 insertions, 88 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index 0f4f14df92..bd9b06ceef 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -1,6 +1,5 @@
if TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD || \
- TARGET_P1021RDB || \
TARGET_P1024RDB || \
TARGET_P2020RDB
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index 2f35622294..875c441051 100644
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -15,14 +15,6 @@ F: configs/P1020RDB-PD_defconfig
F: configs/P1020RDB-PD_NAND_defconfig
F: configs/P1020RDB-PD_SDCARD_defconfig
F: configs/P1020RDB-PD_SPIFLASH_defconfig
-F: configs/P1021RDB-PC_defconfig
-F: configs/P1021RDB-PC_36BIT_defconfig
-F: configs/P1021RDB-PC_36BIT_NAND_defconfig
-F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig
-F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
-F: configs/P1021RDB-PC_NAND_defconfig
-F: configs/P1021RDB-PC_SDCARD_defconfig
-F: configs/P1021RDB-PC_SPIFLASH_defconfig
F: configs/P1024RDB_defconfig
F: configs/P1024RDB_36BIT_defconfig
F: configs/P1024RDB_NAND_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index cbcdf9201b..be803ddf9c 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -14,8 +14,7 @@
#include <asm/fsl_law.h>
#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_P1020RDB_PROTO) || \
- defined(CONFIG_TARGET_P1021RDB)
+#if defined(CONFIG_P1020RDB_PROTO)
/* Micron MT41J256M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 2005944725..4584f0147b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -45,28 +45,9 @@
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-#define GPIO_DDR_RST_PORT 1
-#define GPIO_DDR_RST_PIN 8
-#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
-
-#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
-#endif
-
-#if defined(CONFIG_TARGET_P1021RDB)
-#define PCA_IOPORT_I2C_ADDR 0x23
-#define PCA_IOPORT_OUTPUT_CMD 0x2
-#define PCA_IOPORT_CFG_CMD 0x6
-#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
-#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
-#endif
-
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
- {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
-#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
@@ -119,16 +100,6 @@ void board_gpio_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
- /* reset DDR3 */
- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- udelay(1000);
- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- udelay(1000);
- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
- /* disable CE_PB8 */
- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
-#endif
/* Enable VSC7385 switch */
setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
@@ -372,51 +343,6 @@ int board_eth_init(struct bd_info *bis)
}
#endif
-#if defined(CONFIG_QE) && \
- (defined(CONFIG_TARGET_P1021RDB))
-static void fdt_board_fixup_qe_pins(void *blob)
-{
- unsigned int oldbus;
- u8 val8;
- int node;
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- if (hwconfig("qe")) {
- /* For QE and eLBC pins multiplexing,
- * there is a PCA9555 device on P1025RDB.
- * It control the multiplex pins' functions,
- * and setting the PCA9555 can switch the
- * function between QE and eLBC.
- */
- oldbus = i2c_get_bus_num();
- i2c_set_bus_num(0);
- if (hwconfig("tdm"))
- val8 = PCA_IOPORT_QE_TDM_ENABLE;
- else
- val8 = PCA_IOPORT_QE_PIN_ENABLE;
- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
- 1, &val8, 1);
- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
- 1, &val8, 1);
- i2c_set_bus_num(oldbus);
- /* if run QE TDM, Set ABSWP to implement
- * conversion of addresses in the eLBC.
- */
- if (hwconfig("tdm")) {
- set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
- set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
- setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- }
- } else {
- node = fdt_path_offset(blob, "/qe");
- if (node >= 0)
- fdt_del_node(blob, node);
- }
-
- return;
-}
-#endif
-
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
@@ -444,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
-#if defined(CONFIG_TARGET_P1021RDB)
- fdt_board_fixup_qe_pins(blob);
-#endif
#endif
#if defined(CONFIG_HAS_FSL_DR_USB)