diff options
| author | Ye Li <ye.li@nxp.com> | 2019-01-21 00:37:36 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-01-21 00:41:40 -0800 |
| commit | 71f50000235f58848bad9b2a9f6050bf7d88d592 (patch) | |
| tree | 455f584ba4a6272f9acdac808ac43c6dc9b52e18 /board | |
| parent | adb2db588c5b6401d6769b7766a5ed726d669b2b (diff) | |
MLK-20783 imx8mm: spl: Change VDD_SOC to typical value 0.85V
According to the latest datasheet, software is expected to program
the VDD_SOC voltage to the typical value 0.85V prior to the first
DRAM memory access. At default the VDD_SOC is 0.8V from PMIC BUCK1,
so we have to change it to 0.85V in SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/imx8mm_evk/spl.c | 5 | ||||
| -rw-r--r-- | board/freescale/imx8mm_val/spl.c | 5 |
2 files changed, 8 insertions, 2 deletions
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 8ceea9c36b8..3a91f47f014 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -177,6 +177,9 @@ int power_init_board(void) /* unlock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x1); + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); + /* increase VDD_DRAM to 0.9v for 3Ghz DDR */ pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c index 0d30c826aa8..99144049ea2 100644 --- a/board/freescale/imx8mm_val/spl.c +++ b/board/freescale/imx8mm_val/spl.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -178,6 +178,9 @@ int power_init_board(void) /* unlock the PMIC regs */ pmic_reg_write(p, BD71837_REGLOCK, 0x1); + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); + /* increase VDD_DRAM to 0.9v for 3Ghz DDR */ pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); |