Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips

- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled

7 files changed, 267 insertions, 30 deletions

diff --git a/board/mscc/common/Makefile b/board/mscc/common/Makefile
new file mode 100644
index 00000000000..4f0eded85ab
--- /dev/null
+++ b/board/mscc/common/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_JR2)	:= spi.o
+obj-$(CONFIG_SOC_OCELOT)	:= spi.o
diff --git a/board/mscc/common/spi.c b/board/mscc/common/spi.c
new file mode 100644
index 00000000000..0566fcba5c5
--- /dev/null
+++ b/board/mscc/common/spi.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Coprporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+
+void external_cs_manage(struct udevice *dev, bool enable)
+{
+	u32 cs = spi_chip_select(dev);
+	/* IF_SI0_OWNER, select the owner of the SI interface
+	 * Encoding: 0: SI Slave
+	 *	     1: SI Boot Master
+	 *	     2: SI Master Controller
+	 */
+	if (!enable) {
+		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
+		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
+		       BASE_CFG + ICPU_SW_MODE);
+		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+	} else {
+		writel(0, BASE_CFG + ICPU_SW_MODE);
+		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
+	}
+}
diff --git a/board/mscc/jr2/Kconfig b/board/mscc/jr2/Kconfig
new file mode 100644
index 00000000000..68a2de8ca77
--- /dev/null
+++ b/board/mscc/jr2/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_JR2
+
+config SYS_BOARD
+	default "jr2"
+
+config SYS_CONFIG_NAME
+	default "jr2"
+
+endif
+
diff --git a/board/mscc/jr2/Makefile b/board/mscc/jr2/Makefile
new file mode 100644
index 00000000000..c1db2a90451
--- /dev/null
+++ b/board/mscc/jr2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_JR2)	:= jr2.o
+
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
new file mode 100644
index 00000000000..eac4dcaa10b
--- /dev/null
+++ b/board/mscc/jr2/jr2.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+	BOARD_TYPE_PCB110 = 0xAABBCE00,
+	BOARD_TYPE_PCB111,
+	BOARD_TYPE_PCB112,
+};
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void vcoreiii_gpio_set_alternate(int gpio, int mode)
+{
+	u32 mask;
+	u32 val0, val1;
+	void __iomem *reg0, *reg1;
+
+	if (gpio < 32) {
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
+	} else {
+		gpio -= 32;
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
+	}
+	val0 = readl(reg0);
+	val1 = readl(reg1);
+	if (mode == 1) {
+		writel(val0 | mask, reg0);
+		writel(val1 & ~mask, reg1);
+	} else if (mode == 2) {
+		writel(val0 & ~mask, reg0);
+		writel(val1 | mask, reg1);
+	} else if (mode == 3) {
+		writel(val0 | mask, reg0);
+		writel(val1 | mask, reg1);
+	} else {
+		writel(val0 & ~mask, reg0);
+		writel(val1 & ~mask, reg1);
+	}
+}
+
+static void do_board_detect(void)
+{
+	int i;
+	u16 pval;
+
+	/* MIIM 1 + 2  MDC/MDIO */
+	for (i = 56; i < 60; i++)
+		vcoreiii_gpio_set_alternate(i, 1);
+
+	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
+	    ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
+	} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
+		   ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
+	} else {
+		/* Fall-back */
+		gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
+	}
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB110 &&
+	    strcmp(name, "jr2_pcb110") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB111 &&
+	    strcmp(name, "jr2_pcb111") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB112 &&
+	    strcmp(name, "serval2_pcb112") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 41fc6d56a7d..807c717e33a 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -5,16 +5,20 @@
 
 #include <common.h>
 #include <asm/io.h>
-
-#define MSCC_GPIO_ALT0		0x88
-#define MSCC_GPIO_ALT1		0x8C
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	BOARD_TYPE_PCB090 = 0xAABBCD00,
+	BOARD_TYPE_PCB091,
+};
+
 void board_debug_uart_init(void)
 {
 	/* too early for the pinctrl driver, so configure the UART pins here */
-	setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+	mscc_gpio_set_alternate(30, 1);
+	mscc_gpio_set_alternate(31, 1);
 }
 
 int board_early_init_r(void)
@@ -24,5 +28,45 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF;
+
+	if (chipid == 0x7428 || chipid == 0x7424)
+		gd->board_type = BOARD_TYPE_PCB091;    // Lu10
+	else
+		gd->board_type = BOARD_TYPE_PCB090;    // Lu26
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB090 &&
+	    strcmp(name, "luton_pcb090") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB091 &&
+	    strcmp(name, "luton_pcb091") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
 	return 0;
 }
+#endif
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index d521a619576..0f7a532158e 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -9,39 +9,20 @@
 #include <asm/types.h>
 #include <environment.h>
 #include <spi.h>
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MSCC_GPIO_ALT0		0x54
-#define MSCC_GPIO_ALT1		0x58
-
-void external_cs_manage(struct udevice *dev, bool enable)
-{
-	u32 cs = spi_chip_select(dev);
-	/* IF_SI0_OWNER, select the owner of the SI interface
-	 * Encoding: 0: SI Slave
-	 *           1: SI Boot Master
-	 *           2: SI Master Controller
-	 */
-	if (!enable) {
-		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
-		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
-		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
-	} else {
-		writel(0, BASE_CFG + ICPU_SW_MODE);
-		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
-	}
-}
+enum {
+	BOARD_TYPE_PCB120 = 0xAABBCC00,
+	BOARD_TYPE_PCB123,
+};
 
 void board_debug_uart_init(void)
 {
 	/* too early for the pinctrl driver, so configure the UART pins here */
-	setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
-	clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
+	mscc_gpio_set_alternate(6, 1);
+	mscc_gpio_set_alternate(7, 1);
 }
 
 int board_early_init_r(void)
@@ -54,5 +35,48 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void do_board_detect(void)
+{
+	u16 dummy = 0;
+
+	/* Enable MIIM */
+	mscc_gpio_set_alternate(14, 1);
+	mscc_gpio_set_alternate(15, 1);
+	if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
+		gd->board_type = BOARD_TYPE_PCB120;
+	else
+		gd->board_type = BOARD_TYPE_PCB123;
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB120 &&
+	    strcmp(name, "ocelot_pcb120") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB123 &&
+	    strcmp(name, "ocelot_pcb123") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
 	return 0;
 }
+#endif