diff options
| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2009-10-28 09:30:49 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:24 -0500 |
| commit | 1b81b5d902fec7b67b244991770f085670e7a4a9 (patch) | |
| tree | 5661daa5f606ddaae04d8e678c8051c57e4dd1ab /board | |
| parent | 81bafe293fcea0bdf1f86ade540d6e19a5b378be (diff) | |
DDR support for eSDHC/NAND/eSPI booting
DDR support to boot from NAND/eSDHC/eSPI on P1 & P2 RDB platforms.
Specifically, this support is needed when
L2 Cache size is less than 512K.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/p1_p2_rdb/config.mk | 8 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 3 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 9 |
3 files changed, 19 insertions, 1 deletions
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index 0f7a0487e0..e7829280a3 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -33,13 +33,21 @@ endif ifeq ($(CONFIG_MK_SDCARD), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +ifdef CONFIG_SYS_FSL_BOOT_DDR +RESET_VECTOR_ADDRESS = 0x1107fffc +else RESET_VECTOR_ADDRESS = 0xf8fffffc endif +endif ifeq ($(CONFIG_MK_SPIFLASH), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +ifdef CONFIG_SYS_FSL_BOOT_DDR +RESET_VECTOR_ADDRESS = 0x1107fffc +else RESET_VECTOR_ADDRESS = 0xf8fffffc endif +endif ifndef TEXT_BASE TEXT_BASE = 0xeff80000 diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index fccc4f8f58..cc09046fba 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -246,6 +246,9 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_FSL_BOOT_DDR) + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif dram_size = fixed_sdram(); set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913eaa..c250e3e069 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -78,7 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_INIT_L2_ADDR) /* *I*G - L2SRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -87,6 +88,12 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256K, 1), +#else + /* *I*G - DDR */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1G, 1) +#endif #endif }; |