diff options
author | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-01 12:02:01 -0400 |
---|---|---|
committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-01 12:06:18 -0400 |
commit | 3456a4958ec2ecb2b2e35b1f37039fb28274f182 (patch) | |
tree | bf6aef6608c5410ad8b7e4f49dc2cc58aad22538 /board | |
parent | e1dce181db649aadcf5c83e9459ebf53dd038073 (diff) |
Freescale board patch for MPC5125_TWR board
Diffstat (limited to 'board')
-rw-r--r-- | board/ads5121/ads5121.c | 299 | ||||
-rw-r--r-- | board/ads5121/ads5121_diu.c | 11 | ||||
-rw-r--r-- | board/ads5125/Makefile | 56 | ||||
-rw-r--r-- | board/ads5125/ads5125.c | 515 | ||||
-rw-r--r-- | board/ads5125/config.mk | 28 | ||||
-rw-r--r-- | board/ads5125/u-boot.lds | 122 | ||||
-rw-r--r-- | board/freescale/common/fsl_diu_fb.c | 170 | ||||
-rw-r--r-- | board/freescale/common/fsl_logo_bmp.c | 4 |
8 files changed, 1139 insertions, 66 deletions
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 6c40e94416d..9c1270dcc4d 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2007 DENX Software Engineering * + * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -24,6 +26,7 @@ #include <common.h> #include <mpc512x.h> #include <asm/bitops.h> +#include <asm/io.h> #include <command.h> #include <asm/processor.h> #include <fdt_support.h> @@ -36,10 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_FEC1_EN | \ CLOCK_SCCR1_PATA_EN | \ CLOCK_SCCR1_PCI_EN | \ CLOCK_SCCR1_TPR_EN) @@ -52,6 +56,12 @@ DECLARE_GLOBAL_DATA_PTR; #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) +/* Defines used to Exit Self Refresh after Hibernation */ +#define DDRC_CCR_CLOCK_ON_CMD 0x00001CFF; /* Clock ON */ +#define DDRC_CCR_CKE_HIGH_CMD 0x00003CFF; /* cke high and 200 NOP delay */ +#define DDRC_CCR_SR_CMD 0x00004200; /* Send a Self Refresh */ +#define DDRC_CCR_CMD_MODE_CMD 0x000038FF; /* Set to Normal Mode */ + long int fixed_sdram(void); int board_early_init_f (void) @@ -111,6 +121,40 @@ int board_early_init_f (void) return 0; } +u32 is_micron(void){ + + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + char *mac, *end, macaddr[6]; + u32 brddate, macchk, ismicron; + u32 i; + + /* + * MAC address has serial number with date of manufacture + * Boards made before Nov-08 #1180 use Micron memory; + * 001e59 is the STx vendor # + */ + ismicron = 0; + if (brd_rev >= 0x0400 && (mac = getenv("ethaddr"))) { + for (i=0; i<6; i++) { + macaddr[i] = mac ? + simple_strtoul (mac, &end, 16) : 0; + if (mac) + mac = (*end) ? end+1 : end; + } + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t",brddate); + + if (macchk == 0x001e59 && brddate <= 8111180) + ismicron = 1; + } else if (brd_rev < 0x400) { + ismicron = 1; + } + debug("Using %s Memory settings\n\t", + ismicron ? "Micron" : "Elpida"); + return(ismicron); +} + phys_size_t initdram (int board_type) { u32 msize = 0; @@ -121,12 +165,102 @@ phys_size_t initdram (int board_type) } /* + * hibernation_check -- Check if the board is hibernating and has a kernel + * sleeping in RAM. If so jump there. + */ +void hibernation_check(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + void (*hib_wkup_fnptr)(void); + volatile u32 reg; + u32 use_micron; + +#if DEBUG + printf("RTC_KAR -0x%x\n", im->rtc.kar); +#endif /* DEBUG END */ +#define RTC_KAR_BC6 (1 << 8) + if (im->rtc.kar & RTC_KAR_BC6) { + + printf("\nComing out of Hibernate !\n"); + reg = im->rtc.kar; + + /* setting the DIS_HIB mode bit */ + reg |= 0x00000080; + /* Clear OFF only the WU_SRC sticky Bits */ + reg &= 0xFFFFFFF9; + + /* Writing back to KAR, this will clear the Sticky bit */ + im->rtc.kar = reg; + + /* Disabling the wake-up sources and BC6 bit used for + * Hibernation. + */ + im->rtc.kar &= 0xE0FF02F9; + + use_micron = is_micron(); + + /* Initialize MDDRC */ + if (use_micron) { + im->mddrc.ddr_sys_config = (MDDRC_SYS_CFG_MICRON & + ~(MDDRC_SYS_CFG_CLK_BIT | + MDDRC_SYS_CFG_CKE_BIT)); /* CMD MODE */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_MICRON; + } else { + im->mddrc.ddr_sys_config = (MDDRC_SYS_CFG_ELPIDA & + ~(MDDRC_SYS_CFG_CLK_BIT | + MDDRC_SYS_CFG_CKE_BIT)); /* CMD MODE */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_ELPIDA; + } + + /* Bringing the DDR out of Self-Refresh State */ + /* Clock ON */ + im->mddrc.ddr_compact_command = DDRC_CCR_CLOCK_ON_CMD; + __asm__ __volatile__ ("sync"); + /* cke high and 200 NOP delay */ + im->mddrc.ddr_compact_command = DDRC_CCR_CKE_HIGH_CMD; + __asm__ __volatile__ ("sync"); + /* Send a Self Refresh */ + im->mddrc.ddr_compact_command = DDRC_CCR_SR_CMD; + __asm__ __volatile__ ("sync"); + /* Set to Normal Mode */ + im->mddrc.ddr_compact_command = DDRC_CCR_CMD_MODE_CMD; + __asm__ __volatile__ ("sync"); + + /* Start MDDRC */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0_RUN; + + if (use_micron) + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON_RUN; + else + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA_RUN; + + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("sync"); + + hib_wkup_fnptr = *((void **)0x00000000); + + if (hib_wkup_fnptr != NULL) + hib_wkup_fnptr(); + else { + printf("func pointer is NULL!! returning to normal uboot intialisation\n"); + return; + } + } +} + +/* * fixed sdram init -- the board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ long int fixed_sdram (void) { + u32 use_micron = 0; volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2 (msize); u32 i; @@ -147,68 +281,105 @@ long int fixed_sdram (void) __asm__ __volatile__ ("isync"); /* Enable DDR */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_EN; /* Initialize DDR Priority Manager */ - im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1; - im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2; - im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG; - im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML; - im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML; - im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML; - im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML; - im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU; - im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML; - im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL; - im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL; - im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL; - im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL; - im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; + im->mddrc.prioman_config1 = MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = MDDRCGRP_LUT0_MU; + im->mddrc.lut_table0_main_lower = MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = MDDRCGRP_LUT1_MU; + im->mddrc.lut_table1_main_lower = MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = MDDRCGRP_LUT2_MU; + im->mddrc.lut_table2_main_lower = MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = MDDRCGRP_LUT3_MU; + im->mddrc.lut_table3_main_lower = MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = MDDRCGRP_LUT4_MU; + im->mddrc.lut_table4_main_lower = MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = MDDRCGRP_LUT1_AU; + im->mddrc.lut_table1_alternate_lower = MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = MDDRCGRP_LUT2_AU; + im->mddrc.lut_table2_alternate_lower = MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = MDDRCGRP_LUT3_AU; + im->mddrc.lut_table3_alternate_lower = MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = MDDRCGRP_LUT4_AU; + im->mddrc.lut_table4_alternate_lower = MDDRCGRP_LUT4_AL; + + /* This function will not return if system was hibernating */ + hibernation_check(); + + /* determine which memory settings to use Micron or Elpida */ + use_micron = is_micron(); /* Initialize MDDRC */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG; - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1; - im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2; + if (use_micron) { + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_MICRON; + } else { + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_ELPIDA; + } /* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - + im->mddrc.ddr_command = DDR_NOP; + + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP; + + if (use_micron) { + /* Micron init sequence */ + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + udelay(200); + } else { + /* Elpida init -works for Micron too but runs more slowly */ + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = DDR_RES_DLL; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = ELPIDA_INIT_DEV_OP; + udelay(200); + } + im->mddrc.ddr_command = DDR_OCD_DEFAULT; + im->mddrc.ddr_command = DDR_OCD_EXIT; + im->mddrc.ddr_command = DDR_NOP; + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = DDR_NOP; /* Start MDDRC */ - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0_RUN; + + if (use_micron) + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON_RUN; + else + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA_RUN; return msize; } @@ -225,17 +396,21 @@ int misc_init_r(void) i2c_set_bus_num(2); tmp_val = 0xBF; i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); +#if DEBUG /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n", tmp_val); +#endif tmp_val = 0x10; i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); +#if DEBUG /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n", tmp_val); +#endif #ifdef CONFIG_FSL_DIU_FB #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) @@ -430,3 +605,17 @@ int ide_preinit (void) } #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5121_fsl_nfc_board_cs(int chip) +{ + unsigned char *csreg = (unsigned char *)CONFIG_SYS_CPLD_BASE + 0x09; + u8 v; + + v = in_8(csreg); + v |= 0xf; + v &= ~(1<<chip); + + out_8(csreg, v); +} +#endif diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 41a135314f4..9057bcb846e 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -44,7 +44,7 @@ extern unsigned int FSL_Logo_BMP[]; #endif static int xres, yres; - +#define DEBUG void diu_set_pixel_clock(unsigned int pixclock) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -68,7 +68,9 @@ void diu_set_pixel_clock(unsigned int pixclock) char *valid_bmp(char *addr) { unsigned long h_addr; - +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + return 0; +#else h_addr = simple_strtoul(addr, NULL, 16); if (h_addr < CONFIG_SYS_FLASH_BASE || h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { @@ -79,6 +81,7 @@ char *valid_bmp(char *addr) return 0; } else return (char *)h_addr; +#endif } int ads5121_diu_init(void) @@ -87,8 +90,8 @@ int ads5121_diu_init(void) char *bmp = NULL; char *bmp_env; - xres = 1024; - yres = 768; + xres = 1280; + yres = 720; pixel_format = 0x88883316; debug("ads5121_diu_init\n"); diff --git a/board/ads5125/Makefile b/board/ads5125/Makefile new file mode 100644 index 00000000000..c6e34880309 --- /dev/null +++ b/board/ads5125/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-${CONFIG_FSL_DIU_FB} += ../ads5121/ads5121_diu.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ads5125/ads5125.c b/board/ads5125/ads5125.c new file mode 100644 index 00000000000..2bc5a46e5f6 --- /dev/null +++ b/board/ads5125/ads5125.c @@ -0,0 +1,515 @@ +/* + * (C) Copyright 2008 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#undef DEBUG +#include <common.h> +#include <mpc512x.h> +#include <asm/bitops.h> +#include <asm/io.h> +#include <command.h> +#include <asm/processor.h> +#include <fdt_support.h> +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#endif + +/* PSC Clocks in use */ +#ifdef CONFIG_PSC_CONSOLE2 +#define CLOCK_SCCR1_PSC_EN_BITS ( \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE2) \ + ) +#else +#define CLOCK_SCCR1_PSC_EN_BITS CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) +#endif + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PSC_EN_BITS | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC1_EN | \ + CLOCK_SCCR1_TPR_EN) +#define SCCR1_CFG1_CLOCKS_EN (CLOCK_SCCR1_FEC2_EN) + + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_SDHC1_EN) + +#define SCCR2_CFG0_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_DIU_EN) + +#define SCCR2_CFG1_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_USB2_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +long int fixed_sdram(void); + +static iopin_t ioregs_common_init[] = { + + /* FUNC3=LPC_CS2 Sets Next 3 to LPC pads - done in start.S since + it's CPLD and catch22 here...must read what CFG switch is set + { + IO_CTRL_LPC_AX03, 3, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } */ + /* FUNC1=PSC9_3 Sets Next 2 to PSC9 pads x4f & x50*/ + { + IO_CTRL_I2C1_SCL, 2, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO14 Sets 1 pad */ + { + IO_CTRL_PSC_MCLK_IN, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=IRQ0 Sets 1 pad */ + { + IO_CTRL_PSC1_1, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=CKSTP_OUT Sets 1 pad */ + { + IO_CTRL_PSC1_4, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=I2C1_SCL Sets Next 2 to I2C1 pads */ + { + IO_CTRL_J1850_TX, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* ORs all pads to highest slew rate*/ + { + IO_CTRL_LPC_CLK, IO_CTRL_PSC1_4 - IO_CTRL_LPC_CLK +1, 1, + IO_PIN_FMUX(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; +static iopin_t ioregs_cfg0_init[] = { + /* FUNC2=DIU_LD00 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD00, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=DIU_LD08 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD08, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=DIU_LD16 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD16, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */ + { + IO_CTRL_USB1_DATA0, 12, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + } +}; + +static iopin_t ioregs_cfg1_init[] = { + /* FUNC2=USB1_DATA0 Sets Next 4 to USB1 pads */ + { + IO_CTRL_DIU_CLK, 4, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO32 Sets 1 (2 ??) pad */ + { + IO_CTRL_DIU_LD00, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_DATA4 Sets Next 6 to USB1 pads */ + { + IO_CTRL_DIU_LD02, 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO37 Sets 2 to GPIO pads */ + { + IO_CTRL_DIU_LD08, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_NEXT Sets Next 6 to USB1 and USB2 pads */ + { + IO_CTRL_DIU_LD10, 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=I2C3_SCL Sets Next 2 to I2C3 pads */ + { + IO_CTRL_DIU_LD16, 8, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB2_DATA4 Sets Next 8 to USB2 pads */ + { + IO_CTRL_DIU_LD18, 8, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */ + { + IO_CTRL_USB1_DATA0, 12, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } + /* FUNC3=GPIO10 Sets 1 pad -- COL unused in RMII?? + { + IO_CTRL_USB1_DIR, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } */ +}; +int board_early_init_f (void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 lpcaw; + + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ +/* + out_be32(&im->sysconf.lpcs2aw, CSAW_START(CONFIG_SYS_CPLD_BASE) | + CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)); + out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); +*/ + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lpcaw = in_be32(&im->sysconf.lpcs2aw); + __asm__ __volatile__ ("isync"); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash identification routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); + } else { + /* running from Backup flash */ + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); + } +#endif + /* + * Configure Flash Speed + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); + out_be32((u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG),CONFIG_SYS_CS_ALETIMING); +#endif + /* + * Enable clocks + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (IS_CFG1_SWITCH) { + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN); + } else { + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG0_CLOCKS_EN); + } +#else + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN); +#endif + /* initialize function mux & slew rate IO inter alia on IO Pins */ + /* there are two peripheral options controlled by switch 8 */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (IS_CFG1_SWITCH) + iopin_initialize(ioregs_cfg1_init, + sizeof(ioregs_cfg1_init) / sizeof(ioregs_cfg1_init[0])); + else +#endif + iopin_initialize(ioregs_cfg0_init, + sizeof(ioregs_cfg0_init) / sizeof(ioregs_cfg0_init[0])); + + iopin_initialize(ioregs_common_init, + sizeof(ioregs_common_init) / sizeof(ioregs_common_init[0])); + + /* enable default pins */ + out_8(&im->io_ctrl.regs[IO_CTRL_GBOBE], IOCTRL_GBOBE_ON); + /*enable nfc_ce2 Cloudy*/ + out_8(&im->io_ctrl.regs[IO_CTRL_LPC_ACK_B], 0x3b); + return 0; +} + +phys_size_t initdram (int board_type) +{ + u32 msize = 0; + + msize = fixed_sdram (); + + return msize; +} + +/* + * fixed sdram init -- the board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram (void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; +#if ( BOARD_TYPE!=BOARD_TYPE_5125_MPU) + u32 msize_log2 = __ilog2 (msize); + u32 i; + + /* Initialize IO Control */ + out_8(&im->io_ctrl.regs[IO_CTRL_MEM], IOCTRL_MUX_DDR); + + /* Initialize DDR Local Window */ + out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); + out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + i = im->sysconf.ddrlaw.ar; + __asm__ __volatile__ ("isync"); + + /* Enable DDR */ + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); + + /* Initialize DDR Priority Manager */ + out_be32(&im->mddrc.prioman_config1, MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, MDDRCGRP_LUT4_AL); + + /* Initialize MDDRC */ + out_be32(&im->mddrc.ddr_time_config0, MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2); + /* Initialize DDR */ + for (i = 0; i < 10; i++) + out_be32(&im->mddrc.ddr_command,DDR_NOP); + udelay(1); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_EM2); + out_be32(&im->mddrc.ddr_command,DDR_EM3); + out_be32(&im->mddrc.ddr_command,DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command,DDR_RES_DLL); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + for (i = 0; i < 5; i++) + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command,DDR_OCD_EXIT); + for (i = 0; i < 5; i++) + out_be32(&im->mddrc.ddr_command,DDR_NOP); + udelay(10); + /* Start MDDRC */ + out_be32(&im->mddrc.ddr_time_config0,MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN); +#endif + return msize; +} +#ifdef CONFIG_MISC_INIT_R +struct i2c_init_struct{ + u8 reg_addr; + u8 data; +}; +extern void OnHdmiCableConnected(void); +int misc_init_r(void) +{ + u8 tmp_val; + + extern int ads5121_diu_init(void); +#if(BOARD_TYPE!=BOARD_TYPE_5125_MPU) + if (IS_CFG1_SWITCH) /* no diu in CFG1 */ + return 0; + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + + if (IS_CFG1_SWITCH){ + /* turn on ??? */ + i2c_set_bus_num(2); + } else { + /* Using this for DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + + i2c_set_bus_num(1); + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + } +#endif +#ifdef CONFIG_FSL_DIU_FB +#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) + ads5121_diu_init(); +#endif +#endif +#endif +#if(BOARD_TYPE == BOARD_TYPE_5125_MPU ) +#if (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9034) + /*sil9034 enable */ + struct i2c_init_struct i2c_data[6]= + { + {0x08,0x36}, + {0x0c,0x03}, + {0x0f,0x04}, + {0x33,0x30}, + {0x34,0x00}, + {0x08,0x37}, + }; + for(tmp_val=0;tmp_val<sizeof(i2c_data)/sizeof(i2c_data[0]);tmp_val++) + { + if (i2c_write(0x39, i2c_data[tmp_val].reg_addr, 1, &(i2c_data[tmp_val].data), 1) != 0) + printf("Error writing the chip 0x39 offset %d.\n",i2c_data[tmp_val].data); + } +#elif (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9022A) + /*sil9022a enable DVI signal*/ + struct i2c_init_struct i2c_data[]= + { + {0xc7,0x00}, + {0x1a,0x10}, + {0x1e,0x00}, + {0x1a,0x00}, + }; + for(tmp_val=0;tmp_val<sizeof(i2c_data)/sizeof(i2c_data[0]);tmp_val++) + { + if (i2c_write(0x39, i2c_data[tmp_val].reg_addr, 1, &(i2c_data[tmp_val].data), 1) != 0) + printf("HDMI,Error writing reg==0x%x.\n",i2c_data[tmp_val].reg_addr); + } +#endif +#endif + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ +int checkboard (void) +{ +#if(BOARD_TYPE==BOARD_TYPE_ADS5125) + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); + uchar cpld_rev_min = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x03); + + if (cpld_rev_min != '\0') + printf ("Board: ADS5125 rev. 0x%04x (CPLD rev. 0x%02x.%02x-BETA)\n", + brd_rev, cpld_rev,cpld_rev_min); + else + printf ("Board: ADS5125 rev. 0x%04x (CPLD rev. 0x%02x)\n", + brd_rev, cpld_rev); + if (IS_CFG1_SWITCH) /* CAN1+2, SDHC1, USB1+2, FEC1+2, I2C1+2*/ + printf("Peripheral Option Set 1\n"); + else /* CAN1+2, SDHC1, DIU, USB1, FEC1, I2C1+3*/ + printf("Peripheral Option Set 0\n"); +#else + printf("board: mpc5125_mpu\n"); +#endif + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5125_fsl_nfc_board_cs(int chip) +{ +#if(BOARD_TYPE==BOARD_TYPE_ADS5125) + unsigned char *csreg = (unsigned char *)(CONFIG_SYS_CPLD_BASE + 0x09); + u8 v; + printf("ads5125_fsl_nfc_board_cs chip=%d\n",chip); + v = in_8(csreg); + v |= 0xf; + v &= ~(1<<chip); + + out_8(csreg, v); +#endif +} +#endif + diff --git a/board/ads5125/config.mk b/board/ads5125/config.mk new file mode 100644 index 00000000000..487d2e36481 --- /dev/null +++ b/board/ads5125/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2008 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif +ifndef TEXT_BASE +TEXT_BASE = 0xFFF00000 +endif +LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds diff --git a/board/ads5125/u-boot.lds b/board/ads5125/u-boot.lds new file mode 100644 index 00000000000..482daaa93e8 --- /dev/null +++ b/board/ads5125/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 2fc878be8a7..bc0cf2e8974 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -22,7 +22,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <common.h> #include <i2c.h> #include <malloc.h> @@ -70,7 +69,82 @@ static struct fb_videomode fsl_diu_mode_1024 = { .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED }; +static struct fb_videomode fsl_diu_mode_1024_768_26 = { + .refresh = 26, + .xres = 1024, + .yres = 768, + .pixclock = 36644, + .left_margin = 144, + .right_margin = 144, + .upper_margin = 16, + .lower_margin = 16, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_640_480 = { + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock =39682, + .left_margin = 80, + .right_margin = 80, + .upper_margin =23, + .lower_margin = 22, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_800_600_42= { + .refresh = 42, + .xres = 800, + .yres = 600, + .pixclock =36849, + .left_margin = 112, + .right_margin = 112, + .upper_margin =16, + .lower_margin = 15, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_720x576= { + .refresh = 60, + .xres = 720, + .yres = 576, + .pixclock =27997, + .left_margin = 106, + .right_margin = 106, + .upper_margin =30, + .lower_margin = 30, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_720x480= { + .refresh = 60, + .xres = 720, + .yres = 480, + .pixclock =37000, + .left_margin = 62, + .right_margin = 16, + .upper_margin =32, + .lower_margin = 10, + .hsync_len =60 , + .vsync_len =3, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; static struct fb_videomode fsl_diu_mode_1280 = { .name = "1280x1024-60", .refresh = 60, @@ -86,7 +160,51 @@ static struct fb_videomode fsl_diu_mode_1280 = { .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED }; - +static struct fb_videomode fsl_diu_mode_1280x720 = { + .name = "1280x720-50", + .refresh = 50, + .xres = 1280, + .yres = 720, + .pixclock = 13468, + .left_margin = 440, + .right_margin = 40, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 220, + .vsync_len = 20, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_1280x720_60 = { + .name = "1280x720-60", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, + .left_margin = 40, + .right_margin = 110, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 220, + .vsync_len = 20, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_800x600_60 = { + .name = "800x600-60", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 24996, + .left_margin = 88, + .right_margin = 40, + .upper_margin = 23, + .lower_margin = 1, + .hsync_len = 128, + .vsync_len = 4, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; /* * These are the fields of area descriptor(in DDR memory) for every plane */ @@ -190,7 +308,25 @@ static int fsl_diu_enable_panel(struct fb_info *info); static int fsl_diu_disable_panel(struct fb_info *info); static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); void diu_set_pixel_clock(unsigned int pixclock); +#ifdef CONFIG_ADS5125 +#include <asm/io.h> +#define CONFIG_SYS_IOCTL_ADDR CONFIG_SYS_IMMR+0xA000 +static void mpc5125_cfg_LCD_iopad_init(void) +{ + printf("mpc5125_cfg_LCD_iopad_init\n"); + out_8(CONFIG_SYS_IOCTL_ADDR+0x33,0x43); /* AB9 DIU_LD00*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x34,0x43); /* Y10 DIU_LD01*/ + + out_8(CONFIG_SYS_IOCTL_ADDR+0x3b,0x43); /* W13 DIU_LD08*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x3c,0x43); /* AB12 DIU_LD09*/ + + out_8(CONFIG_SYS_IOCTL_ADDR+0x43,0x43); /* AB15 DIU_LD16*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x44,0x43); /* AB16 DIU_LD17*/ + +} +#endif + int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix, @@ -203,7 +339,9 @@ int fsl_diu_init(int xres, struct fb_var_screeninfo *var = &info->var; unsigned char *gamma_table_base; unsigned int i, j; - +#ifdef CONFIG_ADS5125 + mpc5125_cfg_LCD_iopad_init(); +#endif debug("Enter fsl_diu_init\n"); dr.diu_reg = (struct diu *) (CONFIG_SYS_DIU_ADDR); hw = (struct diu *) dr.diu_reg; @@ -211,9 +349,10 @@ int fsl_diu_init(int xres, disable_lcdc(); if (xres == 1280) { - fsl_diu_mode_db = &fsl_diu_mode_1280; + fsl_diu_mode_db = &fsl_diu_mode_1280x720_60; } else { - fsl_diu_mode_db = &fsl_diu_mode_1024; + + fsl_diu_mode_db = &fsl_diu_mode_720x480; } if (0 == fb_initialized) { @@ -324,7 +463,7 @@ int fsl_diu_init(int xres, var->vsync_len << 11 | /* PW_V */ var->lower_margin; /* FP_V */ - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ + hw->syn_pol = 3; /* SYNC SIGNALS POLARITY */ hw->thresholds = 0x00037800; /* The Thresholds */ hw->int_status = 0; /* INTERRUPT STATUS */ hw->int_mask = 0; /* INT MASK */ @@ -506,6 +645,23 @@ int fsl_diu_display_bmp(unsigned char *bmp, return 0; } if (bpp < 24) { + if(ncolors==0) + { + switch(bpp) + { + case 1: + ncolors=2; + break; + case 4: + ncolors=16; + break; + case 8: + ncolors=256; + break; + default: + break; + } + } for (i = 0, offset = 54; i < ncolors; i++, offset += 4) palette[i] = (bmp[offset+2] << 16) + (bmp[offset+1] << 8) + bmp[offset]; @@ -547,7 +703,7 @@ int fsl_diu_display_bmp(unsigned char *bmp, for (y = height - 1; y >= 0; y--) { fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); for (x = 0; x < width; x++) { - *fb_t++ = palette[ *bitmap++ ]; + *fb_t++ = palette[ *bitmap++ ]|0xff000000; } for (i = (width / 2) % 4; i > 0; i--) bitmap++; diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c index 956dbee9daf..ac5a155f78a 100644 --- a/board/freescale/common/fsl_logo_bmp.c +++ b/board/freescale/common/fsl_logo_bmp.c @@ -27,6 +27,9 @@ * A 340x128x4bpp BMP logo. *--------------------------------------------------------------------------- */ + #if 1 + unsigned int FSL_Logo_BMP[]={}; + #else unsigned int FSL_Logo_BMP[] = { 0x424d765c, 0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000, @@ -876,3 +879,4 @@ unsigned int FSL_Logo_BMP[] = { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, 0x00000000,0x0000babe }; + #endif |