Merge branch 'master' of git://git.denx.de/u-boot-arm

Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR Conflicts: arch/arm/include/asm/arch-omap5/omap.h Signed-off-by: Tom Rini <trini@ti.com>
author: Tom Rini <trini@ti.com> 2013-06-13 15:16:15 -0400
committer: Tom Rini <trini@ti.com> 2013-06-13 15:16:15 -0400
commit: 41341221d12341a2ecfb280142d6478071738fc2 (patch)
tree: 850a87b274b572b65a579474a0aad5e590ca6d61 /board
parent: b7ab8b8ff092ab8214eeb86e8a79573154f448b9 (diff)
parent: 847e6693ccb529bf8346db62876f38f0c4e04ade (diff)
31 files changed, 1208 insertions, 1992 deletions
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index e155556ce2d..8f0f9b8de2e 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -336,7 +336,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile
new file mode 100644
index 00000000000..ac16c1fe3f6
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := cgtqmx6eval.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README
new file mode 100644
index 00000000000..bbf0f75a4d7
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/README
@@ -0,0 +1,29 @@
+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
+qmx6 quad module.
+
+This file contains information for the port of U-Boot to the Congatec
+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+This version of u-boot works only on the SD card. By default, the
+Congatec board can boot only from the SPI-NOR.
+But, with the u-boot version provided with the board you can write boot
+registers to force the board to reboot and boot from the SD slot. If
+"bmode" command is not available from your pre-installed u-boot, these
+instruction will produce the same effect:
+
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
+conga-QMX6 U-Boot > reset
+resetting ...
+
+The the board will reboot and, if you have written your SD correctly
+the board will use u-boot that live into the SD
+
+To copy the resulting u-boot.imx to the SD card:
+
+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
+
+Note: Replace xxx with the device representing the SD card in your system.
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
new file mode 100644
index 00000000000..f70f674b210
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on mx6qsabrelite.c file
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(1, 4));
+		ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+		break;
+	case USDHC4_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+		break;
+	default:
+		printf("Bad USDHC interface\n");
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+	status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+		     fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Conga-QEVAL QMX6 Quad\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index c45c94b4c0d..a4e92541578 100644
--- a/board/davinci/da8xxevm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -39,135 +39,43 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
 #include <asm/io.h>
 #include <nand.h>
 #include <asm/arch/nand_defs.h>
 #include <asm/arch/davinci_misc.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-/* SPI0 pin muxer settings */
-static const struct pinmux_config spi0_pins[] = {
-	{ pinmux(7), 1, 3 },
-	{ pinmux(7), 1, 4 },
-	{ pinmux(7), 1, 5 },
-	{ pinmux(7), 1, 6 },
-	{ pinmux(7), 1, 7 }
-};
-
-/* EMIF-A bus pins for 8-bit NAND support on CS3 */
-static const struct pinmux_config emifa_nand_pins[] = {
-	{ pinmux(13), 1, 6 },
-	{ pinmux(13), 1, 7 },
-	{ pinmux(14), 1, 0 },
-	{ pinmux(14), 1, 1 },
-	{ pinmux(14), 1, 2 },
-	{ pinmux(14), 1, 3 },
-	{ pinmux(14), 1, 4 },
-	{ pinmux(14), 1, 5 },
-	{ pinmux(15), 1, 7 },
-	{ pinmux(16), 1, 0 },
-	{ pinmux(18), 1, 1 },
-	{ pinmux(18), 1, 4 },
-	{ pinmux(18), 1, 5 },
-};
-
-/* EMAC PHY interface pins */
-static const struct pinmux_config emac_pins[] = {
-	{ pinmux(9), 0, 5 },
-	{ pinmux(10), 2, 1 },
-	{ pinmux(10), 2, 2 },
-	{ pinmux(10), 2, 3 },
-	{ pinmux(10), 2, 4 },
-	{ pinmux(10), 2, 5 },
-	{ pinmux(10), 2, 6 },
-	{ pinmux(10), 2, 7 },
-	{ pinmux(11), 2, 0 },
-	{ pinmux(11), 2, 1 },
-};
-
-/* UART pin muxer settings */
-static const struct pinmux_config uart_pins[] = {
-	{ pinmux(8), 2, 7 },
-	{ pinmux(9), 2, 0 }
-};
-
-/* I2C pin muxer settings */
-static const struct pinmux_config i2c_pins[] = {
-	{ pinmux(8), 2, 3 },
-	{ pinmux(8), 2, 4 }
-};
-
-#ifdef CONFIG_USE_NAND
-/* NAND pin muxer settings */
-const struct pinmux_config aemif_pins[] = {
-	{ pinmux(13), 1, 6 },
-	{ pinmux(13), 1, 7 },
-	{ pinmux(14), 1, 0 },
-	{ pinmux(14), 1, 1 },
-	{ pinmux(14), 1, 2 },
-	{ pinmux(14), 1, 3 },
-	{ pinmux(14), 1, 4 },
-	{ pinmux(14), 1, 5 },
-	{ pinmux(14), 1, 6 },
-	{ pinmux(14), 1, 7 },
-	{ pinmux(15), 1, 0 },
-	{ pinmux(15), 1, 1 },
-	{ pinmux(15), 1, 2 },
-	{ pinmux(15), 1, 3 },
-	{ pinmux(15), 1, 4 },
-	{ pinmux(15), 1, 5 },
-	{ pinmux(15), 1, 6 },
-	{ pinmux(15), 1, 7 },
-	{ pinmux(16), 1, 0 },
-	{ pinmux(16), 1, 1 },
-	{ pinmux(16), 1, 2 },
-	{ pinmux(16), 1, 3 },
-	{ pinmux(16), 1, 4 },
-	{ pinmux(16), 1, 5 },
-	{ pinmux(16), 1, 6 },
-	{ pinmux(16), 1, 7 },
-	{ pinmux(17), 1, 0 },
-	{ pinmux(17), 1, 1 },
-	{ pinmux(17), 1, 2 },
-	{ pinmux(17), 1, 3 },
-	{ pinmux(17), 1, 4 },
-	{ pinmux(17), 1, 5 },
-	{ pinmux(17), 1, 6 },
-	{ pinmux(17), 1, 7 },
-	{ pinmux(18), 1, 0 },
-	{ pinmux(18), 1, 1 },
-	{ pinmux(18), 1, 2 },
-	{ pinmux(18), 1, 3 },
-	{ pinmux(18), 1, 4 },
-	{ pinmux(18), 1, 5 },
-	{ pinmux(18), 1, 6 },
-	{ pinmux(18), 1, 7 },
-	{ pinmux(10), 1, 0 }
-};
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
 #endif
 
-
-/* USB0_DRVVBUS pin muxer settings */
-static const struct pinmux_config usb_pins[] = {
-	{ pinmux(9), 1, 1 }
-};
+DECLARE_GLOBAL_DATA_PTR;
 
 static const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_SPI_FLASH
-	PINMUX_ITEM(spi0_pins),
+	PINMUX_ITEM(spi0_pins_base),
+	PINMUX_ITEM(spi0_pins_scs0),
+	PINMUX_ITEM(spi0_pins_ena),
 #endif
-	PINMUX_ITEM(uart_pins),
-	PINMUX_ITEM(i2c_pins),
+	PINMUX_ITEM(uart2_pins_txrx),
+	PINMUX_ITEM(i2c0_pins),
 #ifdef CONFIG_USB_DA8XX
 	PINMUX_ITEM(usb_pins),
 #endif
 #ifdef CONFIG_USE_NAND
-	PINMUX_ITEM(emifa_nand_pins),
-	PINMUX_ITEM(aemif_pins),
+	PINMUX_ITEM(emifa_pins),
+	PINMUX_ITEM(emifa_pins_cs0),
+	PINMUX_ITEM(emifa_pins_cs2),
+	PINMUX_ITEM(emifa_pins_cs3),
 #endif
 #if defined(CONFIG_DRIVER_TI_EMAC)
-	PINMUX_ITEM(emac_pins),
+	PINMUX_ITEM(emac_pins_rmii),
+	PINMUX_ITEM(emac_pins_mdio),
+	PINMUX_ITEM(emac_pins_rmii_clk_source),
+#endif
+#ifdef CONFIG_DAVINCI_MMC
+	PINMUX_ITEM(mmc0_pins_8bit)
 #endif
 };
 
@@ -177,8 +85,31 @@ static const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_EMAC },	/* image download */
 	{ DAVINCI_LPSC_UART2 },	/* console */
 	{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+	{ DAVINCI_LPSC_MMC_SD },
+#endif
+
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.host_caps = MMC_MODE_8BIT,
+	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version = MMC_CTLR_VERSION_2,
 };
 
+int board_mmc_init(bd_t *bis)
+{
+	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+	printf("%x\n", mmc_sd0.input_clk);
+
+	/* Add slot-0 to mmc subsystem */
+	return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
 int board_init(void)
 {
 #ifndef CONFIG_USE_IRQ
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
index 41ba303ec44..d25e2b37ce2 100644
--- a/board/freescale/mx23evk/mx23evk.c
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -43,6 +43,12 @@ int board_early_init_f(void)
 	/* SSP0 clock at 96MHz */
 	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 
+	/* Power on LCD */
+	gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
index 6be8c8d9d0b..fd71f7dc1ba 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -27,6 +27,7 @@
 
 #define	MUX_CONFIG_SSP1	(MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_4MA | MXS_PAD_NOPULL)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
@@ -96,6 +97,37 @@ const iomux_cfg_t iomux_setup[] = {
 	/* Slot Power Enable */
 	MX23_PAD_PWM3__GPIO_1_29 |
 		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* LCD */
+	MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
+	MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
+	MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
 };
 
 #define HW_DRAM_CTL14	(0x38 >> 2)
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index ae6eda343ed..beae0e66e22 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -30,6 +30,7 @@
 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 
 const iomux_cfg_t iomux_setup[] = {
 	/* DUART */
@@ -162,6 +163,38 @@ const iomux_cfg_t iomux_setup[] = {
 	/* I2C */
 	MX28_PAD_I2C0_SCL__I2C0_SCL,
 	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* LCD */
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
+	MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
 };
 
 #define HW_DRAM_CTL29	(0x74 >> 2)
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index de7231bd10b..4edd9f41932 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -59,6 +59,12 @@ int board_early_init_f(void)
 	gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
 #endif
 
+	/* Power on LCD */
+	gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+
+	/* Set contrast to maximum */
+	gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index bfe4868e8a8..2a6e3a91922 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -26,12 +26,14 @@
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,6 +48,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -76,6 +84,45 @@ iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+iomux_v3_cfg_t const i2c3_pads[] = {
+	MX6_PAD_EIM_A24__GPIO_5_4		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const port_exp[] = {
+	MX6_PAD_SD2_DAT0__GPIO_1_15		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static void setup_iomux_enet(void)
 {
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@@ -216,6 +263,16 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	/* I2C 3 Steer */
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 8ce054e4284..862bc3099d1 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -308,7 +308,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile
new file mode 100644
index 00000000000..74162281aee
--- /dev/null
+++ b/board/freescale/vf610twr/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 00000000000..b00d4c1cd38
--- /dev/null
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 00000000000..f14df8b6e19
--- /dev/null
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A14__DDR_A_14,
+		VF610_PAD_DDR_A13__DDR_A_13,
+		VF610_PAD_DDR_A12__DDR_A_12,
+		VF610_PAD_DDR_A11__DDR_A_11,
+		VF610_PAD_DDR_A10__DDR_A_10,
+		VF610_PAD_DDR_A9__DDR_A_9,
+		VF610_PAD_DDR_A8__DDR_A_8,
+		VF610_PAD_DDR_A7__DDR_A_7,
+		VF610_PAD_DDR_A6__DDR_A_6,
+		VF610_PAD_DDR_A5__DDR_A_5,
+		VF610_PAD_DDR_A4__DDR_A_4,
+		VF610_PAD_DDR_A3__DDR_A_3,
+		VF610_PAD_DDR_A2__DDR_A_2,
+		VF610_PAD_DDR_A1__DDR_A_1,
+		VF610_PAD_DDR_BA2__DDR_BA_2,
+		VF610_PAD_DDR_BA1__DDR_BA_1,
+		VF610_PAD_DDR_BA0__DDR_BA_0,
+		VF610_PAD_DDR_CAS__DDR_CAS_B,
+		VF610_PAD_DDR_CKE__DDR_CKE_0,
+		VF610_PAD_DDR_CLK__DDR_CLK_0,
+		VF610_PAD_DDR_CS__DDR_CS_B_0,
+		VF610_PAD_DDR_D15__DDR_D_15,
+		VF610_PAD_DDR_D14__DDR_D_14,
+		VF610_PAD_DDR_D13__DDR_D_13,
+		VF610_PAD_DDR_D12__DDR_D_12,
+		VF610_PAD_DDR_D11__DDR_D_11,
+		VF610_PAD_DDR_D10__DDR_D_10,
+		VF610_PAD_DDR_D9__DDR_D_9,
+		VF610_PAD_DDR_D8__DDR_D_8,
+		VF610_PAD_DDR_D7__DDR_D_7,
+		VF610_PAD_DDR_D6__DDR_D_6,
+		VF610_PAD_DDR_D5__DDR_D_5,
+		VF610_PAD_DDR_D4__DDR_D_4,
+		VF610_PAD_DDR_D3__DDR_D_3,
+		VF610_PAD_DDR_D2__DDR_D_2,
+		VF610_PAD_DDR_D1__DDR_D_1,
+		VF610_PAD_DDR_D0__DDR_D_0,
+		VF610_PAD_DDR_DQM1__DDR_DQM_1,
+		VF610_PAD_DDR_DQM0__DDR_DQM_0,
+		VF610_PAD_DDR_DQS1__DDR_DQS_1,
+		VF610_PAD_DDR_DQS0__DDR_DQS_0,
+		VF610_PAD_DDR_RAS__DDR_RAS_B,
+		VF610_PAD_DDR_WE__DDR_WE_B,
+		VF610_PAD_DDR_ODT1__DDR_ODT_0,
+		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+		&ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+		DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+		&ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+		DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+		&ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+		DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+		&ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+		&ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+	writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+	writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+	writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+		&ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+		&ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+		&ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+		&ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+		&ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+		&ddrmr->cr[132]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+		&ddrmr->cr[139]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+		&ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+	ddr_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	udelay(200);
+}
+
+int dram_init(void)
+{
+	setup_iomux_ddr();
+
+	ddr_ctrl_init();
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	static const iomux_v3_cfg_t enet0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t esdhc1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+		CCM_CCGR0_UART1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+		CCM_CCGR3_ANADIG_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+		CCM_CCGR4_GPC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+		CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+		CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+		CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+		CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: vf610twr\n");
+
+	return 0;
+}
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 923461a3902..7f0330dc038 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -28,7 +28,7 @@
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
 #include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include "errno.h"
 #include <i2c.h>
 #ifdef CONFIG_USB_EHCI
diff --git a/board/ti/omap2420h4/Makefile b/board/icpdas/lp8x4x/Makefile
index cddd7e69850..cbe6aa9ad44 100644
--- a/board/ti/omap2420h4/Makefile
+++ b/board/icpdas/lp8x4x/Makefile
@@ -1,9 +1,7 @@
 #
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# ICPDAS LP-8x4x Support
 #
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -25,15 +23,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= omap2420h4.o mem.o sys_info.o
-SOBJS	:= lowlevel_init.o
+COBJS	:= lp8x4x.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
new file mode 100644
index 00000000000..76f070056b7
--- /dev/null
+++ b/board/icpdas/lp8x4x/lp8x4x.c
@@ -0,0 +1,147 @@
+/*
+ * ICP DAS LP-8x4x Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * adapted from Voipac PXA270 Support by
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	pxa2xx_dram_init();
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef	CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
+#ifdef	CONFIG_CMD_USB
+int usb_board_init(void)
+{
+	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		continue; /* required by checkpath.pl */
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+void lp8x4x_eth1_mac_init(void)
+{
+	u8 eth1addr[8];
+	int i;
+	u8 reg;
+
+	eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
+	if (!is_valid_ether_addr(eth1addr))
+		return;
+
+	for (i = 0, reg = 0x10; i < 6; i++, reg++) {
+		writeb(reg, (u8 *)(DM9000_IO_2));
+		writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	lp8x4x_eth1_mac_init();
+	return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index eda9199bbe9..b9448873c8c 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -160,7 +160,7 @@ int ethernet_present(void)
 }
 #endif
 
-int initialize_unit_leds(void)
+static int initialize_unit_leds(void)
 {
 	/*
 	 * Init the unit LEDs per default they all are
@@ -181,7 +181,7 @@ int initialize_unit_leds(void)
 }
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT)
-void set_bootcount_addr(void)
+static void set_bootcount_addr(void)
 {
 	uchar buf[32];
 	unsigned int bootcountaddr;
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index 8347cf9ce94..5c730988883 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -31,7 +31,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <spartan3.h>
 #include <asm/gpio.h>
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 73bf8531650..638cc4d68b2 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -514,6 +514,7 @@ int board_eth_init(bd_t *bis)
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 
+#ifdef CONFIG_DRIVER_TI_CPSW
 	if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -529,6 +530,7 @@ int board_eth_init(bd_t *bis)
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
+#endif
 
 	/*
 	 *
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 04c95fd376a..338a241ce78 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -29,19 +29,29 @@
 #include <asm/arch/mux_dra7xx.h>
 
 const struct pad_conf_entry core_padconf_array_essential[] = {
-	{MMC1_CLK, (PTU | IEN | M0)},	/* MMC1_CLK */
-	{MMC1_CMD, (PTU | IEN | M0)},   /* MMC1_CMD */
-	{MMC1_DAT0, (PTU | IEN | M0)},  /* MMC1_DAT0 */
-	{MMC1_DAT1, (PTU | IEN | M0)},  /* MMC1_DAT1 */
-	{MMC1_DAT2, (PTU | IEN | M0)},  /* MMC1_DAT2 */
-	{MMC1_DAT3, (PTU | IEN | M0)},  /* MMC1_DAT3 */
-	{MMC1_SDCD, (PTU | IEN | M0)},  /* MMC1_SDCD */
-	{MMC1_SDWP, (PTU | IEN | M0)},  /* MMC1_SDWP */
-	{UART1_RXD, (PTU | IEN | M0)},  /* UART1_RXD */
-	{UART1_TXD, (M0)},              /* UART1_TXD */
-	{UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
-	{UART1_RTSN, (M0)},             /* UART1_RTSN */
-	{I2C1_SDA, (PTU | IEN | M0)},   /* I2C1_SDA */
-	{I2C1_SCL, (PTU | IEN | M0)},   /* I2C1_SCL */
+	{MMC1_CLK, (IEN | PTU | PDIS | M0)},	/* MMC1_CLK */
+	{MMC1_CMD, (IEN | PTU | PDIS | M0)},	/* MMC1_CMD */
+	{MMC1_DAT0, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT0 */
+	{MMC1_DAT1, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT1 */
+	{MMC1_DAT2, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT2 */
+	{MMC1_DAT3, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT3 */
+	{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+	{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+	{GPMC_A19, (IEN | PTU | PDIS | M1)},	/* mmc2_dat4 */
+	{GPMC_A20, (IEN | PTU | PDIS | M1)},	/* mmc2_dat5 */
+	{GPMC_A21, (IEN | PTU | PDIS | M1)},	/* mmc2_dat6 */
+	{GPMC_A22, (IEN | PTU | PDIS | M1)},	/* mmc2_dat7 */
+	{GPMC_A23, (IEN | PTU | PDIS | M1)},	/* mmc2_clk */
+	{GPMC_A24, (IEN | PTU | PDIS | M1)},	/* mmc2_dat0 */
+	{GPMC_A25, (IEN | PTU | PDIS | M1)},	/* mmc2_dat1 */
+	{GPMC_A26, (IEN | PTU | PDIS | M1)},	/* mmc2_dat2 */
+	{GPMC_A27, (IEN | PTU | PDIS | M1)},	/* mmc2_dat3 */
+	{GPMC_CS1, (IEN | PTU | PDIS | M1)},	/* mmm2_cmd */
+	{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+	{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+	{UART1_CTSN, (IEN | PTU | PDIS | M3)},	/* UART1_CTSN */
+	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
+	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
+	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk
deleted file mode 100644
index e5dff69a15f..00000000000
--- a/board/ti/omap2420h4/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-#CONFIG_SYS_TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-#CONFIG_SYS_TEXT_BASE = 0x40270000
-
-
-# Handy to get symbols to debug ROM version.
-#CONFIG_SYS_TEXT_BASE = 0x0
-CONFIG_SYS_TEXT_BASE = 0x08000000
-#CONFIG_SYS_TEXT_BASE = 0x04000000
diff --git a/board/ti/omap2420h4/lowlevel_init.S b/board/ti/omap2420h4/lowlevel_init.S
deleted file mode 100644
index 731c552e7a2..00000000000
--- a/board/ti/omap2420h4/lowlevel_init.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
-	/* Copy DPLL code into SRAM */
-	adr	r0, go_to_speed		/* get addr of clock setting code */
-	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
-	mov	r1, r1			/* r1 <- dest address (passed in) */
-	add	r2, r2, r0		/* r2 <- source end address */
-next2:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next2
-	mov	pc, lr			/* back to caller */
-
-/* ****************************************************************************
- *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- *		 -executed from SRAM.
- *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- *  R2 = dpll value
- *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
-	sub	sp, sp, #0x4 /* get some stack space */
-	str	r4, [sp]     /* save r4's value */
-
-	/* move into fast relock bypass */
-	ldr	r8, pll_ctl_add
-	mov	r4, #0x2
-	str	r4, [r8]
-	ldr	r4, pll_stat
-block:
-	ldr	r8, [r4]	/* wait for bypass to take effect */
-	and	r8, r8, #0x3
-	cmp	r8, #0x1
-	bne	block
-
-	/* set new dpll dividers _after_ in bypass */
-	ldr	r4, pll_div_add
-	ldr	r8, pll_div_val
-	str	r8, [r4]
-
-	/* now prepare GPMC (flash) for new dpll speed */
-	/* flash needs to be stable when we jump back to it */
-	ldr	r4, cfg3_0_addr
-	ldr	r8, cfg3_0_val
-	str	r8, [r4]
-	ldr	r4, cfg4_0_addr
-	ldr	r8, cfg4_0_val
-	str	r8, [r4]
-	ldr	r4, cfg1_0_addr
-	ldr	r8, [r4]
-	orr	r8, r8, #0x3	 /* up gpmc divider */
-	str	r8, [r4]
-
-	/* setup to 2x loop though code.  The first loop pre-loads the
-	 * icache, the 2nd commits the prcm config, and locks the dpll
-	 */
-	mov	r4, #0x1000	 /* spin spin spin */
-	mov	r8, #0x4	 /* first pass condition & set registers */
-	cmp	r8, #0x4
-2:
-	ldrne	r8, [r3]	 /* DPLL lock check */
-	and	r8, r8, #0x7
-	cmp	r8, #0x2
-	beq	4f
-3:
-	subeq	r8, r8, #0x1
-	streq	r8, [r0]	 /* commit dividers (2nd time) */
-	nop
-lloop1:
-	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
-	nop
-	cmp	r4, #0x0
-	bne	lloop1
-	mov	r4, #0x40000
-	cmp	r8, #0x1
-	nop
-	streq	r2, [r1]	/* lock dpll (2nd time) */
-	nop
-lloop2:
-	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
-	nop
-	cmp	r4, #0x0
-	bne	lloop2
-	mov	r4, #0x40000
-	cmp	r8, #0x1
-	nop
-	ldreq	r8, [r3]	 /* get lock condition for dpll */
-	cmp	r8, #0x4	 /* first time though? */
-	bne	2b
-	moveq	r8, #0x2	 /* set to dpll check condition. */
-	beq	3b		 /* if condition not true branch */
-4:
-	ldr	r4, [sp]
-	add	sp, sp, #0x4	 /* return stack space */
-	mov	pc, lr		 /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
-    .word  GPMC_CONFIG3_0
-cfg3_0_val:
-    .word  H4_24XX_GPMC_CONFIG3_0
-cfg4_0_addr:
-    .word  GPMC_CONFIG4_0
-cfg4_0_val:
-    .word  H4_24XX_GPMC_CONFIG4_0
-cfg1_0_addr:
-    .word  GPMC_CONFIG1_0
-pll_ctl_add:
-    .word CM_CLKEN_PLL
-pll_stat:
-    .word CM_IDLEST_CKGEN
-pll_div_add:
-    .word CM_CLKSEL1_PLL
-pll_div_val:
-    .word DPLL_VAL	/* DPLL setting (300MHz default) */
-
-.globl lowlevel_init
-lowlevel_init:
-	ldr	sp,	SRAM_STACK
-	str	ip,	[sp]	/* stash old link register */
-	mov	ip,	lr	/* save link reg across call */
-	bl	s_init		/* go setup pll,mux,memory */
-	ldr	ip,	[sp]	/* restore save ip */
-	mov	lr,	ip	/* restore link reg */
-
-	/* map interrupt controller */
-	ldr	r0,	VAL_INTH_SETUP
-	mcr	p15, 0, r0, c15, c2, 4
-
-	/* back to arch calling code */
-	mov	pc,	lr
-
-	/* the literal pools origin */
-	.ltorg
-
-REG_CONTROL_STATUS:
-	.word CONTROL_STATUS
-VAL_INTH_SETUP:
-	.word PERIFERAL_PORT_BASE
-SRAM_STACK:
-	.word LOW_LEVEL_SRAM_STACK
diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c
deleted file mode 100644
index ba3f12adeda..00000000000
--- a/board/ti/omap2420h4/mem.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in 12MHz bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*********************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
- *   -- called from SRAM, or Flash (using temp SRAM stack).
- *********************************************************************************/
-void prcm_init(void)
-{
-	u32 div;
-	void (*f_lock_pll) (u32, u32, u32, u32);
-	extern void *_end_vect, *_start;
-
-	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
-
-	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
-	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
-	__raw_writel(0, CM_ICLKEN1_CORE);
-	__raw_writel(0, CM_ICLKEN2_CORE);
-
-	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
-	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
-	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
-	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
-
-	div = BUS_DIV;
-	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
-	sdelay(1000);
-
-	if(running_in_sram()){
-		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
-		* but then comes back.  If running from Flash this sequence kills you, thus you need
-		* to run it using CONFIG_PARTIAL_SRAM.
-		*/
-		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
-		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
-		sdelay(1000);
-		/* set clock selection and dpll dividers. */
-		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
-		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
-		sdelay(10000);
-		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
-		sdelay(10000);
-		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
-	}else if(running_in_flash()){
-		/* if running from flash, need to jump to small relocated code area in SRAM.
-		 * This is the only safe spot to do configurations from.
-		 */
-		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
-	}
-
-	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
-	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
-	sdelay(1000);
-}
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontigious support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(SDRC_CS0_OSET);
-	size /= SZ_32M;  /* find size to offset CS1 */
-	a_add_high = (size & 3) << 8;   /* set up low field */
-	a_add_low = (size & 0x3C) >> 2; /* set up high field */
-	__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
-
-}
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in gussing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(void)
-{
-	u32 val1, val2;
-	u32 pattern = 0x12345678;
-
-	__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400);   /* clear pos A */
-	__raw_writel(pattern, OMAP2420_SDRC_CS0);    /* pattern to pos B */
-	__raw_writel(0x0,OMAP2420_SDRC_CS0+4);       /* remove pattern off the bus */
-	val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
-	val2 = __raw_readl(OMAP2420_SDRC_CS0);       /* get val2 */
-
-	if ((val1 != 0) || (val2 != pattern))        /* see if pos A value changed*/
-		return(0);
-	else
-		return(1);
-}
-
-
-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-	#define EARLY_INIT 1
-	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);  /* only init up first bank here */
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -called from low level code with stack only.
- *  -code sets up SDRAM timing and muxing for 2422 or 2420.
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  This is a bit ugly, but should handle all memory moduels
- *   used with the H4. The first time though this code from s_init()
- *   we configure the first chip select.  Later on we come back and
- *   will configure the 2nd chip select if it exists.
- *
- **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early)
-{
-	u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
-	sdrc_data_t *sdata;	 /* do not change type */
-	u32 a, b, r;
-
-	static const sdrc_data_t sdrc_2422 =
-	{
-		H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
-		H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
-		0, H4_2422_SDRC_DLLAB_CTRL
-	};
-	static const sdrc_data_t sdrc_2420 =
-	{
-		H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
-		H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
-		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
-		H4_2420_SDRC_DLLAB_CTRL
-	};
-
-	if (offset == SDRC_CS0_OSET)
-		cs0 = common = 1;  /* int regs shared between both chip select */
-
-	cpu = get_cpu_type();
-	rev = get_cpu_rev();
-
-	/* warning generated, though code generation is correct. this may bite later,
-	 * but is ok for now. there is only so much C code you can do on stack only
-	 * operation.
-	 */
-	if (cpu == CPU_2422){
-		sdata = (sdrc_data_t *)&sdrc_2422;
-		pass_type = STACKED;
-	} else{
-		sdata = (sdrc_data_t *)&sdrc_2420;
-		pass_type = IP_DDR;
-	}
-
-	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
-
-	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
-		if(mtype == DDR_COMBO){
-			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
-			pass_type = COMBO_DDR; /* CS1 config */
-			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
-		}
-		if(rev != CPU_2420_2422_ES1)	/* for es2 and above smooth things out */
-			make_cs1_contiguous();
-	}
-
-next_mem_type:
-	if (common) {	/* do a SDRC reset between types to clear regs*/
-		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
-		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
-		__raw_writel(0, SDRC_SYSCONFIG);		/* clear soft reset */
-		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
-#ifdef POWER_SAVE
-		__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
-		__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
-		__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
-#endif
-	}
-
-	if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
-		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
-	else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
-		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
-	} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
-		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
-	}
-
-	a = sdata->sdrc_actim_ctrla_0;
-	b = sdata->sdrc_actim_ctrlb_0;
-	r = sdata->sdrc_dllab_ctrl;
-
-	/* work around ES1 DDR issues */
-	if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
-		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
-		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
-		r = H4_242x_SDRC_RFR_CTRL_ES1;
-	}
-
-	if (cs0) {
-		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
-		__raw_writel(b, SDRC_ACTIM_CTRLB_0);
-	} else {
-		__raw_writel(a, SDRC_ACTIM_CTRLA_1);
-		__raw_writel(b, SDRC_ACTIM_CTRLB_1);
-	}
-	__raw_writel(r, SDRC_RFR_CTRL+offset);
-
-	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
-	__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
-	sdelay(5000);  /* susposed to be 100us per design spec for mddr/msdr */
-	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
-	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
-	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
-
-	/*
-	 * CSx SDRC Mode Register
-	 * Burst length = (4 - DDR) (2-SDR)
-	 * Serial mode
-	 * CAS latency = x
-	 */
-	if(pass_type == IP_SDR)
-		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
-	else
-		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
-
-	/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
-	if (rev == CPU_2420_2422_ES1){
-		dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
-		__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
-			,SMS_CLASS_ARB0);/* enable bust complete for lcd */
-	}
-	else
-		dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
-
-	/* enable & load up DLL with good value for 75MHz, and set phase to 90
-	 * ES1 recommends 90 phase, ES2 recommends 72 phase.
-	 */
-	if (common && (pass_type != IP_SDR)) {
-		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
-		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
-	}
-	sdelay(90000);
-
-	if(mem_ok())
-		return; /* STACKED, other configued type */
-	++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
-	goto next_mem_type;
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	u32 mux=0, mtype, mwidth, rev, tval;
-
-	rev  = get_cpu_rev();
-	if (rev == CPU_2420_2422_ES1)
-		tval = 1;
-	else
-		tval = 0;  /* disable bit switched meaning */
-
-	/* global settings */
-	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
-	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
-	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CONFIG_SYS_NAND_BOOT
-	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
-#else
-	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
-#endif
-
-	/* discover bus connection from sysboot */
-	if (is_gpmc_muxed() == GPMC_MUXED)
-		mux = BIT9;
-	mtype = get_gpmc0_type();
-	mwidth = get_gpmc0_width();
-
-	/* setup cs0 */
-	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
-	sdelay(1000);
-
-#ifdef CONFIG_SYS_NAND_BOOT
-	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
-#else
-	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
-#endif
-
-#ifdef PRCM_CONFIG_III
-	__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
-#endif
-	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
-	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
-#ifdef PRCM_CONFIG_III
-	__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
-	__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
-#endif
-	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
-	sdelay(2000);
-
-	/* setup cs1 */
-	__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
-	sdelay(1000);
-	__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
-	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
-	sdelay(2000);
-}
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
deleted file mode 100644
index 532e989bac3..00000000000
--- a/board/ti/omap2420h4/omap2420h4.c
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/mem.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void wait_for_command_complete(unsigned int wd_base);
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
-	gpmc_init(); /* in SRAM or SDRM, finish GPMC */
-
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;		/* board id for linux */
-	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);	/* adress of boot parameters */
-
-	return 0;
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- *  general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
-	/* if GP device unlock device SRAM for general use */
-	if (get_device_type() == GP_DEVICE) {
-		__raw_writel(0xFF, A_REQINFOPERM0);
-		__raw_writel(0xCFDE, A_READPERM0);
-		__raw_writel(0xCFDE, A_WRITEPERM0);
-	}
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with sram stack.
- **********************************************************/
-void s_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	watchdog_init();
-	set_muxconf_regs();
-	delay(100);
-	try_unlock_sram();
-
-	if(!in_sdram)
-		prcm_init();
-
-	peripheral_enable();
-	icache_enable();
-	if (!in_sdram)
-		sdrc_init();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
-	ether_init(); /* better done here so timers are init'ed */
-	return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
-	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
-	* The ROM takes care of the secure one. Of the 3 GP ones,
-	* 1 can reset us directly, the other 2 only generate MPU interrupts.
-	*/
-	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
-	wait_for_command_complete(WD2_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
-	__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
-	wait_for_command_complete(WD3_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
-
-	__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
-	wait_for_command_complete(WD4_BASE);
-	__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
-#endif
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
-	int pending = 1;
-	do {
-		pending = __raw_readl(wd_base+WWPS);
-	} while (pending);
-}
-
-/*******************************************************************
- * Routine:ether_init
- * Description: take the Ethernet controller out of reset and wait
- *		   for the EEPROM load to complete.
- ******************************************************************/
-void ether_init (void)
-{
-#ifdef CONFIG_LAN91C96
-	int cnt = 20;
-
-	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
-
-	__raw_writew(0x0, LAN_RESET_REGISTER);
-	do {
-		__raw_writew(0x1, LAN_RESET_REGISTER);
-		udelay (100);
-		if (cnt == 0)
-			goto h4reset_err_out;
-		--cnt;
-	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-
-	cnt = 20;
-
-	do {
-		__raw_writew(0x0, LAN_RESET_REGISTER);
-		udelay (100);
-		if (cnt == 0)
-			goto h4reset_err_out;
-		--cnt;
-	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
-	udelay (1000);
-
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (1000);
-
-	h4reset_err_out:
-	return;
-#endif
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
-	unsigned int size0=0,size1=0;
-	u32 mtype, btype;
-	u8 chg_on = 0x5; /* enable charge of back up battery */
-	u8 vmode_on = 0x8C;
-	#define NOT_EARLY 0
-
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
-
-	btype = get_board_type();
-	mtype = get_mem_type();
-
-	display_board_info(btype);
-	if (btype == BOARD_H4_MENELAUS){
-		update_mux(btype,mtype); /* combo part on menelaus */
-		i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
-		i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
-	}
-
-	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
-		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
-	}
-	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
-	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	unsigned int size0, size1;
-	u32 rev;
-
-	rev = get_cpu_rev();
-	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
-	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
-	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
-		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	else /* ES2 and above can remap at 32MB granularity */
-		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
-	gd->bd->bi_dram[1].size = size1;
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-}
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- *              specific to the hardware
- *********************************************************/
-void set_muxconf_regs (void)
-{
-	muxSetupSDRC();
-	muxSetupGPMC();
-	muxSetupUsb0();
-	muxSetupUart3();
-	muxSetupI2C1();
-	muxSetupUART1();
-	muxSetupLCD();
-	muxSetupCamera();
-	muxSetupMMCSD();
-	muxSetupTouchScreen();
-	muxSetupHDQ();
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void peripheral_enable(void)
-{
-	unsigned int v, if_clks=0, func_clks=0;
-
-	/* Enable GP2 timer.*/
-	if_clks |= BIT4;
-	func_clks |= BIT4;
-	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP2420_GPT2 */
-	__raw_writel(v, CM_CLKSEL2_CORE);
-	__raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CONFIG_SYS_NS16550
-	/* Enable UART1 clock */
-	func_clks |= BIT21;
-	if_clks |= BIT21;
-#endif
-	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
-	__raw_writel(v,CM_ICLKEN1_CORE );
-	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
-	__raw_writel(v, CM_FCLKEN1_CORE);
-	delay(1000);
-
-#ifndef KERNEL_UPDATED
-	{
-#define V1 0xffffffff
-#define V2 0x00000007
-
-		__raw_writel(V1, CM_FCLKEN1_CORE);
-		__raw_writel(V2, CM_FCLKEN2_CORE);
-		__raw_writel(V1, CM_ICLKEN1_CORE);
-		__raw_writel(V1, CM_ICLKEN2_CORE);
-	}
-#endif
-}
-
-/****************************************
- * Routine: muxSetupUsb0   (ostboot)
- * Description: Setup usb muxing
- *****************************************/
-void muxSetupUsb0(void)
-{
-	volatile uint8   *MuxConfigReg;
-	volatile uint32  *otgCtrlReg;
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	/* setup for USB VBus detection */
-	otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
-	*otgCtrlReg |= 0x00040000; /* bit 18 */
-}
-
-/****************************************
- * Routine: muxSetupUart3   (ostboot)
- * Description: Setup uart3 muxing
- *****************************************/
-void muxSetupUart3(void)
-{
-	volatile uint8 *MuxConfigReg;
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
-	*MuxConfigReg &= (uint8)(~0x1F);
-
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
-	*MuxConfigReg &= (uint8)(~0x1F);
-}
-
-/****************************************
- * Routine: muxSetupI2C1   (ostboot)
- * Description: Setup i2c muxing
- *****************************************/
-void muxSetupI2C1(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* I2C1 Clock pin configuration, PIN = M19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* I2C1 Data pin configuration, PIN = L15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* Pull-up required on data line */
-	/* external pull-up already present. */
-	/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
-}
-
-/****************************************
- * Routine: muxSetupUART1  (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-void muxSetupUART1(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* UART1_CTS pin configuration, PIN = D21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RTS pin configuration, PIN = H21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_TX pin configuration, PIN = L20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* UART1_RX pin configuration, PIN = T21 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupLCD   (ostboot)
- * Description: Setup lcd muxing
- *****************************************/
-void muxSetupLCD(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* LCD_D0 pin configuration, PIN = Y7  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D1 pin configuration, PIN = P10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D2 pin configuration, PIN = V8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D3 pin configuration, PIN = Y8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D4 pin configuration, PIN = W8  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D5 pin configuration, PIN = R10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D6 pin configuration, PIN = Y9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D7 pin configuration, PIN = V9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D8 pin configuration, PIN = W9  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D9 pin configuration, PIN = P11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D10 pin configuration, PIN = V10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D11 pin configuration, PIN = Y10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D12 pin configuration, PIN = W10 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D13 pin configuration, PIN = R11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D14 pin configuration, PIN = V11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D15 pin configuration, PIN = W11 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D16 pin configuration, PIN = P12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_D17 pin configuration, PIN = R12 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_PCLK pin configuration,   PIN = W6   */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_VSYNC pin configuration,  PIN = V7  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_HSYNC pin configuration,  PIN = Y6  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* LCD_ACBIAS pin configuration, PIN = W7 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupCamera  (ostboot)
- * Description: Setup camera muxing
- *****************************************/
-void muxSetupCamera(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
-	/* CAM_RST is connected through the I2C IO expander.*/
-	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
-	/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
-
-	/* CAMERA_XCLK  pin configuration, PIN = U3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_LCLK  pin configuration, PIN = V5 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
-	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_VSYNC pin configuration, PIN = U2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_HSYNC pin configuration, PIN = T3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT0 pin configuration, PIN = T4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT1 pin configuration, PIN = V2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT2 pin configuration, PIN = V3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT3 pin configuration, PIN = U4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT4 pin configuration, PIN = W2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT5 pin configuration, PIN = V4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT6 pin configuration, PIN = W3 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* CAMERA_DAT9 pin configuration, PIN = V6 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupMMCSD (ostboot)
- * Description: set up MMC muxing
- *****************************************/
-void muxSetupMMCSD(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* SDMMC_CLKI pin configuration,  PIN = H15 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CLKO pin configuration,  PIN = G19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CMD pin configuration,   PIN = H18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-	/* External pull-ups are present. */
-	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
-	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SDMMC_CDIR pin configuration,  PIN = G18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
-	/* MMC_CD for 2422IP=K1 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-
-	/* MMC_WP pin configuration,      PIN = B4  */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/******************************************
- * Routine: muxSetupTouchScreen (ostboot)
- * Description:  Set up touch screen muxing
- *******************************************/
-void muxSetupTouchScreen(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* SPI1_CLK pin configuration,  PIN = U18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MOSI pin configuration, PIN = V20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_MISO pin configuration, PIN = T18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* SPI1_nCS0 pin configuration, PIN = U19 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
-	/* PEN_IRQ pin configuration,   PIN = P20 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
-				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupHDQ (ostboot)
- * Description: setup 1wire mux
- *****************************************/
-void muxSetupHDQ(void)
-{
-	volatile unsigned char  *MuxConfigReg;
-
-	/* HDQ_SIO pin configuration,  PIN = N18 */
-	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
-				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/***************************************************************
- * Routine: muxSetupGPMC (ostboot)
- * Description: Configures balls which cam up in protected mode
- ***************************************************************/
-void muxSetupGPMC(void)
-{
-	volatile uint8 *MuxConfigReg;
-	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
-
-	/* gpmc_io_dir */
-	*MCR = 0x19000000;
-
-	/* NOR FLASH CS0 */
-	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
-				   *MuxConfigReg = 0x01 ;
-
-	/* MPDB(Multi Port Debug Port) CS1 */
-	/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
-				   *MuxConfigReg = 0x00 ;
-}
-
-/****************************************************************
- * Routine: muxSetupSDRC  (ostboot)
- * Description: Configures balls which come up in protected mode
- ****************************************************************/
-void muxSetupSDRC(void)
-{
-	volatile uint8 *MuxConfigReg;
-
-	/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
-				   *MuxConfigReg = 0x00 ;
-
-	/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3	Pull/up - N/A */
-	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
-				   *MuxConfigReg = 0x00;
-
-	if (get_cpu_type() == CPU_2422) {
-		MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
-					   *MuxConfigReg = 0x1b;
-	}
-}
-
-/*****************************************************************************
- * Routine: update_mux()
- * Description: Update balls which are different beween boards.  All should be
- *              updated to match functionaly.  However, I'm only updating ones
- *              which I'll be using for now.  When power comes into play they
- *              all need updating.
- *****************************************************************************/
-void update_mux(u32 btype,u32 mtype)
-{
-	u32 cpu, base = OMAP2420_CTRL_BASE;
-	cpu = get_cpu_type();
-
-	if (btype == BOARD_H4_MENELAUS) {
-		if (cpu == CPU_2420) {
-			/* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
-			__raw_writeb(0x3, base+0x30);
-			/* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
-			__raw_writeb(0x3, base+0xa3);
-			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
-			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
-			/* PIN = M1 (HSUSBOTG) */
-			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
-			__raw_writeb(0x3, base+0x9d);
-			/* PIN = U32, (WLAN_CLKREQ) */
-			/* PIN = Y11, WLAN */
-			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
-			__raw_writeb(0x3, base+0xe7);
-			/* PIN = AA8, mDOC */
-			/* PIN = AA10, BT */
-			/* PIN = AA13, WLAN */
-			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 HHUSB */
-			/* PIN = H19 HSUSB */
-			/* PIN = W13, P13, R13, W16 ... */
-			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
-			__raw_writeb(0x3, base+0xde);
-			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
-			__raw_writeb(0x0, base+0x12c);
-			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
-			__raw_writeb(0x0, base+0x136);
-		} else if (cpu == CPU_2422) {
-			/* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
-			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
-			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
-			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
-			__raw_writeb(0x0, base+0x92);
-			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
-			/* PIN = M1 (HSUSBOTG) */
-			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
-			__raw_writeb(0x3, base+0x10c);
-			/* PIN = U32, (WLAN_CLKREQ) */
-			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
-			__raw_writeb(0x3, base+0x30);
-			/* PIN = AA8, mDOC */
-			/* PIN = AA10, BT */
-			/* PIN = AA12, WLAN */
-			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 HHUSB */
-			/* PIN = H19 HSUSB */
-			/* PIN = W13, P13, R13, W16 ... */
-			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
-			__raw_writeb(0x3, base+0xde);
-			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
-			__raw_writeb(0x0, base+0x12c);
-			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
-			__raw_writeb(0x0, base+0x136);
-		}
-
-	} else if (btype == BOARD_H4_SDP) {
-		if (cpu == CPU_2420) {
-			/* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
-			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
-			/* Pin = Y11 VLNQ */
-			/* Pin = AA4 VLNQ */
-			/* Pin = AA6 VLNQ */
-			/* Pin = AA8 VLNQ */
-			/* Pin = AA10 VLNQ */
-			/* Pin = AA12 VLNQ */
-			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 MDOC_nDMAREQ */
-			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
-			__raw_writeb(0x3, base+0x114);
-			/* PIN = W13, V12, P13, R13, W19, W16 ... */
-			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
-		} else if (cpu == CPU_2422) {
-			/* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
-			/* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
-			/* Pin = Y11 VLNQ */
-			/* Pin = AA4 VLNQ */
-			/* Pin = AA6 VLNQ */
-			/* Pin = AA8 VLNQ */
-			/* Pin = AA10 VLNQ */
-			/* Pin = AA12 VLNQ */
-			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x10e);
-			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
-			__raw_writeb(0x3, base+0x110);
-			/* PIN = J15 MDOC_nDMAREQ */
-			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
-			__raw_writeb(0x3, base+0x114);
-			/* PIN = W13, V12, P13, R13, W19, W16 ... */
-			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
-		}
-	}
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c
deleted file mode 100644
index b12011e04ab..00000000000
--- a/board/ti/omap2420h4/sys_info.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h>  /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <i2c.h>
-
-/**************************************************************************
- * get_prod_id() - get id info from chips
- ***************************************************************************/
-static u32 get_prod_id(void)
-{
-	u32 p;
-	p = __raw_readl(PRODUCTION_ID); /* get production ID */
-	return((p & CPU_242X_PID_MASK) >> 16);
-}
-
-/**************************************************************************
- * get_cpu_type() - low level get cpu type
- * - no C globals yet.
- * - just looking to say if this is a 2422 or 2420 or ...
- * - to start with we will look at switch settings..
- * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
- *   (mux for 2420, non-mux for 2422).
- ***************************************************************************/
-u32 get_cpu_type(void)
-{
-	u32 v;
-
-	switch(get_prod_id()){
-		case 1:;/* 2420 */
-		case 2: return(CPU_2420); break; /* 2420 pop */
-		case 4: return(CPU_2422); break;
-		case 8: return(CPU_2423); break;
-		default: break;  /* early 2420/2422's unmarked */
-	}
-
-	v = __raw_readl(TAP_IDCODE_REG);
-	v &= CPU_24XX_ID_MASK;
-	if (v == CPU_2420_CHIPID) {	  /* currently 2420 and 2422 have same id */
-		if (is_gpmc_muxed() == GPMC_MUXED)	  /* if mux'ed */
-			return(CPU_2420);
-		else
-			return(CPU_2422);
-	} else
-		return(CPU_2420); /* don't know, say 2420 */
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
-	u32 v;
-	v = __raw_readl(TAP_IDCODE_REG);
-	v = v >> 28;
-	return(v+1);  /* currently 2422 and 2420 match up */
-}
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
-	if(*burst == H4_2420_SDRC_MR_0_SDR)
-		return(1);
-	return(0);
-}
-
-/***********************************************************
- * get_mem_type() - identify type of mDDR part used.
- * 2422 uses stacked DDR, 2 parts CS0/CS1.
- * 2420 may have 1 or 2, no good way to know...only init 1...
- * when eeprom data is up we can select 1 more.
- *************************************************************/
-u32 get_mem_type(void)
-{
-	u32 cpu, sdr = is_mem_sdr();
-
-	cpu = get_cpu_type();
-	if (cpu == CPU_2422 || cpu == CPU_2423)
-		return(DDR_STACKED);
-
-	if(get_prod_id() == 0x2)
-		return(XDR_POP);
-
-	if (get_board_type() == BOARD_H4_MENELAUS)
-		if(sdr)
-			return(SDR_DISCRETE);
-		else
-			return(DDR_COMBO);
-	else
-		if(sdr) /* SDP + SDR kit */
-			return(SDR_DISCRETE);
-		else
-			return(DDR_DISCRETE); /* origional SDP */
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
-{
-	u32 size;
-	size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
-	size &= 0x2FF;   /* remove unwanted bits */
-	size *= SZ_2M;   /* find size in MB */
-	return(size);
-}
-
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
- *      when they are available we can get info from there.  This should
- *      be correct of all known boards up until today.
- ************************************************************************/
-u32 get_board_type(void)
-{
-	if (i2c_probe(I2C_MENELAUS) == 0)
-		return(BOARD_H4_MENELAUS);
-	else
-		return(BOARD_H4_SDP);
-}
-
-/******************************************************************
- * get_sysboot_value() - get init word settings (dip switch on h4)
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
-	return(0x00000FFF & __raw_readl(CONTROL_STATUS));
-}
-
-/***************************************************************************
- *  get_gpmc0_base() - Return current address hardware will be
- *     fetching from. The below effectively gives what is correct, its a bit
- *   mis-leading compared to the TRM.  For the most general case the mask
- *   needs to be also taken into account this does work in practice.
- *   - for u-boot we currently map:
- *       -- 0 to nothing,
- *       -- 4 to flash
- *       -- 8 to enent
- *       -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
-	u32 b;
-
-	b = __raw_readl(GPMC_CONFIG7_0);
-	b &= 0x1F;	 /* keep base [5:0] */
-	b = b << 24; /* ret 0x0b000000 */
-	return(b);
-}
-
-/*****************************************************************
- *  is_gpmc_muxed() - tells if address/data lines are multiplexed
- *****************************************************************/
-u32 is_gpmc_muxed(void)
-{
-	u32 mux;
-	mux = get_sysboot_value();
-	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
-		return(GPMC_MUXED); /* NAND Boot mode */
-	if (mux & BIT1)	   /* if mux'ed */
-		return(GPMC_MUXED);
-	else
-		return(GPMC_NONMUXED);
-}
-
-/************************************************************************
- *  get_gpmc0_type() - read sysboot lines to see type of memory attached
- ************************************************************************/
-u32 get_gpmc0_type(void)
-{
-	u32 type;
-	type = get_sysboot_value();
-	if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
-		return(TYPE_NAND);
-	else
-		return(TYPE_NOR);
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
-	u32 width;
-	width = get_sysboot_value();
-	if ((width & 0xF) == (BIT3|BIT2))
-		return(WIDTH_8BIT);
-	else
-		return(WIDTH_16BIT);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- *   volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
-	u32 i = 0, val;
-	do {
-		++i;
-		val = __raw_readl(read_addr) & read_bit_mask;
-		if (val == match_value)
-			return(1);
-		if (i==bound)
-			return(0);
-	} while (1);
-}
-
-/*********************************************************************
- *  display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
-	static const char cpu_2420 [] = "2420";   /* cpu type */
-	static const char cpu_2422 [] = "2422";
-	static const char cpu_2423 [] = "2423";
-	static const char db_men [] = "Menelaus"; /* board type */
-	static const char db_ip [] = "IP";
-	static const char mem_sdr [] = "mSDR";    /* memory type */
-	static const char mem_ddr [] = "mDDR";
-	static const char t_tst [] = "TST";	    /* security level */
-	static const char t_emu [] = "EMU";
-	static const char t_hs [] = "HS";
-	static const char t_gp [] = "GP";
-	static const char unk [] = "?";
-
-	const char *cpu_s, *db_s, *mem_s, *sec_s;
-	u32 cpu, rev, sec;
-
-	rev = get_cpu_rev();
-	cpu = get_cpu_type();
-	sec = get_device_type();
-
-	if(is_mem_sdr())
-		mem_s = mem_sdr;
-	else
-		mem_s = mem_ddr;
-
-	if(cpu == CPU_2423)
-		cpu_s = cpu_2423;
-	else if (cpu == CPU_2422)
-		cpu_s = cpu_2422;
-	else
-		cpu_s = cpu_2420;
-
-	if(btype ==  BOARD_H4_MENELAUS)
-		db_s = db_men;
-	else
-		db_s = db_ip;
-
-	switch(sec){
-		case TST_DEVICE: sec_s = t_tst; break;
-		case EMU_DEVICE: sec_s = t_emu; break;
-		case HS_DEVICE:  sec_s = t_hs; break;
-		case GP_DEVICE:  sec_s = t_gp; break;
-		default: sec_s = unk;
-	}
-
-	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
-	printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- *          0 = 242x IP platform (first 2xx boards)
- *          1 = 242x Menelaus platfrom.
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	u32 rev = 0;
-	u32 btype = get_board_type();
-
-	if (btype == BOARD_H4_MENELAUS){
-		rev = 1;
-	}
-	return(rev);
-}
-
-/********************************************************
- *  get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
-	u32  val;
-	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
-	val &= 0xF0000000;
-	val >>= 28;
-	return(val);
-}
-
-/********************************************************
- *  get_base2(); get 2upper addr of current execution
- *******************************************************/
-u32 get_base2(void)
-{
-	u32  val;
-	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
-	val &= 0xFF000000;
-	val >>= 24;
-	return(val);
-}
-
-/********************************************************
- *  running_in_flash() - tell if currently running in
- *   flash.
- *******************************************************/
-u32 running_in_flash(void)
-{
-	if (get_base() < 4)
-		return(1);  /* in flash */
-	return(0); /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- *  running_in_sram() - tell if currently running in
- *   sram.
- *******************************************************/
-u32 running_in_sram(void)
-{
-	if (get_base() == 4)
-		return(1);  /* in SRAM */
-	return(0); /* running in FLASH or SDRAM */
-}
-/********************************************************
- *  running_in_sdram() - tell if currently running in
- *   flash.
- *******************************************************/
-u32 running_in_sdram(void)
-{
-	if (get_base() > 4)
-		return(1);  /* in sdram */
-	return(0); /* running in SRAM or FLASH */
-}
-
-/*************************************************************
- *  running_from_internal_boot() - am I a signed NOR image.
- *************************************************************/
-u32 running_from_internal_boot(void)
-{
-	u32 v, base;
-
-	v = get_sysboot_value() & BIT3;
-	base = get_base2();
-	/* if running at mask rom flash address and
-	 * sysboot3 says this was an internal boot
-	 */
-	if ((base == 0x08) && v)
-		return(1);
-	else
-		return(0);
-}
-
-/*************************************************************
- *  get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
-	int mode;
-	mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
-	return(mode >>= 8);
-}
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 46db1bfe664..90046e896e6 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -71,22 +71,26 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
 		   sizeof(core_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
 void set_muxconf_regs_non_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_non_essential,
 		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_non_essential,
 		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 2bbe392d811..90ae29e7c64 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 
@@ -139,16 +139,18 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
 		   sizeof(core_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
 	if (omap_revision() >= OMAP4460_ES1_0)
-		do_set_mux(CONTROL_PADCONF_WKUP,
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
 				 wkup_padconf_array_essential_4460,
 				 sizeof(wkup_padconf_array_essential_4460) /
 				 sizeof(struct pad_conf_entry));
@@ -156,27 +158,29 @@ void set_muxconf_regs_essential(void)
 
 void set_muxconf_regs_non_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_non_essential,
 		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
 	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux(CONTROL_PADCONF_CORE,
+		do_set_mux((*ctrl)->control_padconf_core_base,
 				core_padconf_array_non_essential_4430,
 				sizeof(core_padconf_array_non_essential_4430) /
 				sizeof(struct pad_conf_entry));
 	else
-		do_set_mux(CONTROL_PADCONF_CORE,
+		do_set_mux((*ctrl)->control_padconf_core_base,
 				core_padconf_array_non_essential_4460,
 				sizeof(core_padconf_array_non_essential_4460) /
 				sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_non_essential,
 		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
 	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux(CONTROL_PADCONF_WKUP,
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
 				wkup_padconf_array_non_essential_4430,
 				sizeof(wkup_padconf_array_non_essential_4430) /
 				sizeof(struct pad_conf_entry));
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 4c1a4f7e786..5dd1ba3cb43 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -72,16 +72,18 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
 		   sizeof(core_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
 
 	if (omap_revision() >= OMAP4460_ES1_0)
-		do_set_mux(CONTROL_PADCONF_WKUP,
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
 				 wkup_padconf_array_essential_4460,
 				 sizeof(wkup_padconf_array_essential_4460) /
 				 sizeof(struct pad_conf_entry));
@@ -89,16 +91,18 @@ void set_muxconf_regs_essential(void)
 
 void set_muxconf_regs_non_essential(void)
 {
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_non_essential,
 		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_non_essential,
 		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
 	if (omap_revision() < OMAP4460_ES1_0) {
-		do_set_mux(CONTROL_PADCONF_WKUP,
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
 			wkup_padconf_array_non_essential_4430,
 			sizeof(wkup_padconf_array_non_essential_4430) /
 			sizeof(struct pad_conf_entry));
diff --git a/board/wandboard/README b/board/wandboard/README
index e0b0b330208..ce83bbe4c5e 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -14,12 +14,12 @@ Building U-boot for Wandboard
 
 To build U-Boot for the Wandboard Dual Lite version:
 
-$ make wanboard_dl_config
+$ make wandboard_dl_config
 $ make
 
 To build U-Boot for the Wandboard Solo version:
 
-$ make wanboard_solo_config
+$ make wandboard_solo_config
 $ make
 
 Flashing U-boot into the SD card
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index bb983528b9a..5666cbf26f2 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -10,9 +10,11 @@
  */
 
 #include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -21,9 +23,11 @@
 #include <asm/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <ipu_pixfmt.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <linux/fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -206,6 +210,88 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(void)
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+static struct fb_videomode const hdmi = {
+	.name           = "HDMI",
+	.refresh        = 60,
+	.xres           = 1024,
+	.yres           = 768,
+	.pixclock       = 15385,
+	.left_margin    = 220,
+	.right_margin   = 40,
+	.upper_margin   = 21,
+	.lower_margin   = 7,
+	.hsync_len      = 60,
+	.vsync_len      = 10,
+	.sync           = FB_SYNC_EXT,
+	.vmode          = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+	int ret;
+
+	ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+
+	if (ret)
+		printf("HDMI cannot be configured: %d\n", ret);
+
+	enable_hdmi();
+
+	return ret;
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on IPU clock */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+		| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+
+	/* clear HDMI PHY reset */
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+		| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+		| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+	      | (CHSCCDR_PODF_DIVIDE_BY_3
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+	      | (CHSCCDR_IPU_PRE_CLK_540M_PFD
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
 int board_eth_init(bd_t *bis)
 {
 	int ret;
@@ -222,9 +308,21 @@ int board_eth_init(bd_t *bis)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
 	return 0;
 }
 
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
author	Tom Rini <trini@ti.com>	2013-06-13 15:16:15 -0400
committer	Tom Rini <trini@ti.com>	2013-06-13 15:16:15 -0400
commit	41341221d12341a2ecfb280142d6478071738fc2 (patch)
tree	850a87b274b572b65a579474a0aad5e590ca6d61 /board
parent	b7ab8b8ff092ab8214eeb86e8a79573154f448b9 (diff)
parent	847e6693ccb529bf8346db62876f38f0c4e04ade (diff)