Modify device tree files for Link

The flash map needs to be reshuffled because the Ivy Bridge MRC does
not fit into the room Sandy bridge MRC used to fit in (512K are
required instead of 256K), so the entire boot stub gets now 1M instead
of 512K.

link.dts is also being modified as appropriate.

BUG=chrome-os-partner:6707
TEST=none

Change-Id: I2cb6ef9319d57233f5254063d7c35f135fd34a52
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/12605
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>

2 files changed, 26 insertions, 27 deletions

diff --git a/board/chromebook-x86/coreboot/flashmap-8mb_1mbRom.dtsi b/board/chromebook-x86/coreboot/flashmap-8mb_1mbRom.dtsi
index 53c66e5dab..aa0e3bc4c0 100644
--- a/board/chromebook-x86/coreboot/flashmap-8mb_1mbRom.dtsi
+++ b/board/chromebook-x86/coreboot/flashmap-8mb_1mbRom.dtsi
@@ -64,7 +64,7 @@
 		 */
 		coreboot-extra@0 {
 			label = "coreboot-extra";
-			reg = <0x00200000 0x001ff000>;
+			reg = <0x00200000 0x0017f000>;
 			type = "wiped";
 			wipe-value = [ff];
 		};
@@ -73,7 +73,7 @@
 		rw-mrc-cache@0 {
 			label = "rw-mrc-cache";
 			/* Alignment: 4k (for updating) */
-			reg = <0x003ff000 0x00001000>;
+			reg = <0x0037f000 0x00001000>;
 			type = "wiped";
 			wipe-value = [ff];
 		};
@@ -82,7 +82,7 @@
 		rw-vpd@0 {
 			label = "rw-vpd";
 			/* Alignment: 4k (for updating) */
-			reg = <0x00400000 0x00001000>;
+			reg = <0x00380000 0x00001000>;
 			type = "wiped";
 			wipe-value = [ff];
 		};
@@ -94,7 +94,7 @@
 			 * Anything in this range may be updated in recovery.
 			 */
 			label = "rw-shared";
-			reg = <0x00401000 0x0001b000>;
+			reg = <0x00381000 0x0001b000>;
 		};
 		shared-data@0 {
 			label = "shared-data";
@@ -102,7 +102,7 @@
 			 * Alignment: 4k (for random read/write).
 			 * RW firmware can put calibration data here.
 			 */
-			reg = <0x00401000 0x0001b000>;
+			reg = <0x00381000 0x0001b000>;
 			type = "wiped";
 			wipe-value = [00];
 		};
@@ -114,7 +114,7 @@
 			 * Alignment: 4k, and must occupy bottom of U-Boot
 			 * firmware -- check CONFIG_ENV_OFFSET
 			 */
-			reg = <0x0041c000 0x00004000>;
+			reg = <0x0039c000 0x00004000>;
 
 			/*
 			 * We could put the dev environment here, but U-Boot has
@@ -129,7 +129,7 @@
 		rw-a@0 {
 			label = "rw-section-a";
 			/* Alignment: 4k (for updating) */
-			reg = <0x00420000 0x000f0000>;
+			reg = <0x003a0000 0x000f0000>;
 		};
 		rw-a-vblock@0 {
 			label = "vblock-a";
@@ -137,7 +137,7 @@
 			 * Alignment: 4k (for updating) and must be in start of
 			 * each RW_SECTION.
 			 */
-			reg = <0x00420000 0x00010000>;
+			reg = <0x003a0000 0x00010000>;
 			type = "keyblock boot";
 			keyblock = "firmware.keyblock";
 			signprivate = "firmware_data_key.vbprivk";
@@ -148,13 +148,13 @@
 		rw-a-boot@0 {
 			/* Alignment: no requirement (yet). */
 			label = "fw-main-a";
-			reg = <0x00430000 0x000dffc0>;
+			reg = <0x003b0000 0x000dffc0>;
 			type = "blob boot";
 		};
 		rw-a-firmware-id@0 {
 			/* Alignment: no requirement. */
 			label = "rw-fwid-a";
-			reg = <0x0050ffc0 0x00000040>;
+			reg = <0x0048ffc0 0x00000040>;
 			read-only;
 			type = "blobstring fwid";
 		};
@@ -163,7 +163,7 @@
 		rw-b@0 {
 			label = "rw-section-b";
 			/* Alignment: 4k (for updating) */
-			reg = <0x00510000 0x000f0000>;
+			reg = <0x00490000 0x000f0000>;
 		};
 		rw-b-vblock@0 {
 			label = "vblock-b";
@@ -171,7 +171,7 @@
 			 * Alignment: 4k (for updating) and must be in start of
 			 * each RW_SECTION.
 			 */
-			reg = <0x00510000 0x00010000>;
+			reg = <0x00490000 0x00010000>;
 			type = "keyblock boot";
 			keyblock = "firmware.keyblock";
 			signprivate = "firmware_data_key.vbprivk";
@@ -182,13 +182,13 @@
 		rw-b-boot@0 {
 			label = "fw-main-b";
 			/* Alignment: no requirement (yet). */
-			reg = <0x00520000 0x000dffc0>;
+			reg = <0x004a0000 0x000dffc0>;
 			type = "blob boot";
 		};
 		rw-b-firmware-id@0 {
 			label = "rw-fwid-b";
 			/* Alignment: no requirement. */
-			reg = <0x005fffc0 0x00000040>;
+			reg = <0x0057ffc0 0x00000040>;
 			read-only;
 			type = "blobstring fwid";
 		};
@@ -198,7 +198,7 @@
 			label = "ro-vpd";
 
 			/* VPD offset must be aligned to 4K bytes */
-			reg = <0x00600000 0x00020000>;
+			reg = <0x00580000 0x00020000>;
 			read-only;
 			type = "wiped";
 			wipe-value = [ff];
@@ -207,7 +207,7 @@
                 /* ---- Section: Read-only ---- */
 		ro-section@0 {
                         label = "ro-section";
-			reg = <0x00620000 0x001e0000>;
+			reg = <0x005a0000 0x001e0000>;
 			read-only;
 		};
 		ro-fmap@0 {
@@ -220,7 +220,7 @@
 			 * 256KB.
 			 */
 
-			reg = <0x00670000 0x00000800>;
+			reg = <0x005f0000 0x00000800>;
 			read-only;
 			type = "fmap";
 			ver-major = <1>;
@@ -228,33 +228,33 @@
 		};
 		ro-firmware-id@0 {
 			label = "ro-frid";
-			reg = <0x00670800 0x00000040>;
+			reg = <0x005f0800 0x00000040>;
 			read-only;
 			type = "blobstring fwid";
 		};
 		ro-recovery@0 {
 			/* Deprecated section */
 			label = "recovery";
-			reg = <0x00680000 0x00080000>;
+			reg = <0x00600000 0x00080000>;
 			read-only;
 		};
 		ro-data@0 {
 		        /* Currently unused, simply for padding */
 			label = "ro-data";
-			reg = <0x00700000 0x00040000>;
+			reg = <0x00680000 0x00040000>;
 			read-only;
 		};
 		ro-gbb@0 {
 			label = "gbb";
 
 			/* GBB offset must be aligned to 4K bytes */
-			reg = <0x00740000 0x00040000>;
+			reg = <0x006c0000 0x00040000>;
 			read-only;
 			type = "blob gbb";
 		};
 		ro-boot@0 {
 			label = "boot-stub";
-			reg = <0x00780000 0x00080000>; /* 512 KB */
+			reg = <0x00700000 0x00100000>; /* 1 MB */
 			read-only;
 			type = "blob signed";
 		};
diff --git a/board/chromebook-x86/coreboot/link.dts b/board/chromebook-x86/coreboot/link.dts
index 9ba8bda77c..ea6afe2e00 100644
--- a/board/chromebook-x86/coreboot/link.dts
+++ b/board/chromebook-x86/coreboot/link.dts
@@ -2,14 +2,13 @@
 
 /include/ "skeleton.dtsi"
 /include/ "chromeos.dtsi"
-/include/ "flashmap-8mb.dtsi"
+/include/ "flashmap-8mb_1mbRom.dtsi"
 
 / {
-	model = "Google Stumpy";
-	compatible = "google,stumpy", "intel,celeron-sandybridge";
+	model = "Google Link";
+	compatible = "google,link", "intel,celeron-ivybridge";
 
 	config {
-		hwid = "X86 STUMPY TEST 0128";
-		skip-i8042 = <1>;
+	       hwid = "X86 LINK TEST 6638";
 	};
 };