Expand flash map to maximize size for U-Boot

This increases the size of RO U-Boot to 1MiB and RW U-Boot to 950KiB
to maximize flexibility in the future. We cannot change the FMAP later
so this is trying to cover for all eventualities.

Note: This commit does not affect Seaboard, since it only has 2MiB
of SPI flash.

BUG=chromium-os:19238
TEST=build for Aebl, Kaen, Seaboard

Change-Id: Ifb57fec75eba06eb9946e6a8d7e8100bd5e92c57
Reviewed-on: http://gerrit.chromium.org/gerrit/6227
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

4 files changed, 149 insertions, 68 deletions

diff --git a/board/nvidia/seaboard/flashmap-ro-1mb.dtsi b/board/nvidia/seaboard/flashmap-ro-1mb.dtsi
new file mode 100644
index 0000000000..1fc6812786
--- /dev/null
+++ b/board/nvidia/seaboard/flashmap-ro-1mb.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * This is a sub-fmap embedded into twostop fmap. This sub-fmap defines
+ * the layout of the R/O portion.
+ *
+ * The R/O blobs only consumes 1 MB space so that it could be possible to
+ * squeeze the final image (R/O + R/W) into 2 MB space. As a result, even if
+ * the target machine has a 4 MB flash chip and enables write-protect for the
+ * first 2 MB space, only the first 1 MB will contain R/O blobs and the rest
+ * 1 MB will be empty.
+ */
+
+/ {
+	/*
+	 * Labels have been selected to be to compatible with existing tools,
+	 * even thought the terminology may be a little different on ARM.
+	 * Names will be capitalized and hyphen converted to underscore by
+	 * cros_bundle_firmware.
+	 */
+	flash@0 {
+                /* ---- Section: Read-only ---- */
+		ro-section@0 {
+                        label = "ro-section";
+			reg = <0x00000000 0x000f0000>;
+			read-only;
+		};
+
+		ro-boot@0 {
+			label = "boot-stub";
+			reg = <0x00000000 0x000aff00>; /* 703 KB */
+			read-only;
+			type = "blob signed";
+		};
+		ro-recovery@aff00 {
+			/* Deprecated section */
+			label = "recovery";
+			reg = <0x000aff00 0x00000000>;
+			read-only;
+		};
+		ro-firmware-id@aff00 {
+			label = "ro-frid";
+			reg = <0x000aff00 0x00000100>;
+			read-only;
+			type = "blobstring fwid";
+		};
+		ro-fmap@b0000 {
+			label = "fmap";
+
+			/* We encourage to align FMAP partition in as large
+			 * block as possible so that flashrom can find it soon.
+			 * For example, aligning to 512KB is better than to
+			 * 256KB. */
+
+			reg = <0x000b0000 0x00001000>;
+			read-only;
+			type = "fmap";
+			ver-major = <1>;
+			ver-minor = <0>;
+		};
+		ro-gbb@b1000 {
+			label = "gbb";
+
+			/* GBB offset must be aligned to 4K bytes */
+			reg = <0x000b1000 0x0003f000>;
+			read-only;
+			type = "blob gbb";
+		};
+		ro-data@f0000 {
+		        /* Currently unused, simply for padding */
+			label = "ro-data";
+			reg = <0x000f0000 0x00000000>;
+			read-only;
+		};
+
+                /* ---- Section: Vital-product data (VPD) ---- */
+		ro-vpd@f0000 {
+			label = "ro-vpd";
+
+			/* VPD offset must be aligned to 4K bytes */
+			reg = <0x000f0000 0x00010000>;
+			read-only;
+			type = "wiped";
+			wipe-value = [ff];
+		};
+	};
+};
diff --git a/board/nvidia/seaboard/flashmap-ro.dtsi b/board/nvidia/seaboard/flashmap-ro.dtsi
index 1fc6812786..2a8778f64e 100644
--- a/board/nvidia/seaboard/flashmap-ro.dtsi
+++ b/board/nvidia/seaboard/flashmap-ro.dtsi
@@ -7,12 +7,6 @@
 /*
  * This is a sub-fmap embedded into twostop fmap. This sub-fmap defines
  * the layout of the R/O portion.
- *
- * The R/O blobs only consumes 1 MB space so that it could be possible to
- * squeeze the final image (R/O + R/W) into 2 MB space. As a result, even if
- * the target machine has a 4 MB flash chip and enables write-protect for the
- * first 2 MB space, only the first 1 MB will contain R/O blobs and the rest
- * 1 MB will be empty.
  */
 
 / {
@@ -24,31 +18,25 @@
 	 */
 	flash@0 {
                 /* ---- Section: Read-only ---- */
-		ro-section@0 {
+		ro-section {
                         label = "ro-section";
-			reg = <0x00000000 0x000f0000>;
+			reg = <0x00000000 0x001f0000>;
 			read-only;
 		};
 
-		ro-boot@0 {
+		ro-boot {
 			label = "boot-stub";
-			reg = <0x00000000 0x000aff00>; /* 703 KB */
+			reg = <0x00000000 0x00100000>; /* 1 MB */
 			read-only;
 			type = "blob signed";
 		};
-		ro-recovery@aff00 {
+		ro-recovery {
 			/* Deprecated section */
 			label = "recovery";
-			reg = <0x000aff00 0x00000000>;
+			reg = <0x00100000 0x00000000>;
 			read-only;
 		};
-		ro-firmware-id@aff00 {
-			label = "ro-frid";
-			reg = <0x000aff00 0x00000100>;
-			read-only;
-			type = "blobstring fwid";
-		};
-		ro-fmap@b0000 {
+		ro-fmap {
 			label = "fmap";
 
 			/* We encourage to align FMAP partition in as large
@@ -56,33 +44,39 @@
 			 * For example, aligning to 512KB is better than to
 			 * 256KB. */
 
-			reg = <0x000b0000 0x00001000>;
+			reg = <0x00100000 0x00001000>;
 			read-only;
 			type = "fmap";
 			ver-major = <1>;
 			ver-minor = <0>;
 		};
-		ro-gbb@b1000 {
+		ro-firmware-id {
+			label = "ro-frid";
+			reg = <0x00101000 0x00000100>;
+			read-only;
+			type = "blobstring fwid";
+		};
+		ro-gbb {
 			label = "gbb";
 
 			/* GBB offset must be aligned to 4K bytes */
-			reg = <0x000b1000 0x0003f000>;
+			reg = <0x00110000 0x00080000>;
 			read-only;
 			type = "blob gbb";
 		};
-		ro-data@f0000 {
+		ro-data {
 		        /* Currently unused, simply for padding */
 			label = "ro-data";
-			reg = <0x000f0000 0x00000000>;
+			reg = <0x00190000 0x00060000>;
 			read-only;
 		};
 
                 /* ---- Section: Vital-product data (VPD) ---- */
-		ro-vpd@f0000 {
+		ro-vpd {
 			label = "ro-vpd";
 
 			/* VPD offset must be aligned to 4K bytes */
-			reg = <0x000f0000 0x00010000>;
+			reg = <0x001f0000 0x00010000>;
 			read-only;
 			type = "wiped";
 			wipe-value = [ff];
diff --git a/board/nvidia/seaboard/flashmap-twostop-2mb.dtsi b/board/nvidia/seaboard/flashmap-twostop-2mb.dtsi
index 42d4628cc0..77915c3e08 100644
--- a/board/nvidia/seaboard/flashmap-twostop-2mb.dtsi
+++ b/board/nvidia/seaboard/flashmap-twostop-2mb.dtsi
@@ -13,7 +13,8 @@
 * All sections will be marked static in the fmap.
 */
 
-/include/ "flashmap-ro.dtsi"
+/* Use the small 1MB flash map when we only have 2MB of SPI flash */
+/include/ "flashmap-ro-1mb.dtsi"
 
 / {
 	flash@0 {
diff --git a/board/nvidia/seaboard/flashmap-twostop-4mb.dtsi b/board/nvidia/seaboard/flashmap-twostop-4mb.dtsi
index b902ff3a83..857e5585ad 100644
--- a/board/nvidia/seaboard/flashmap-twostop-4mb.dtsi
+++ b/board/nvidia/seaboard/flashmap-twostop-4mb.dtsi
@@ -15,22 +15,6 @@
 
 /include/ "flashmap-ro.dtsi"
 
-/*
-* TODO: Although we can squeeze R/O and R/W blobs into 2 MB, we do not do
-* so because:
-*
-* - (A minor reason) Not every 4 MB flash chip can write-protect just the
-*   first 1 MB.
-*
-* - (The main reason) We do not know how many tools or scripts implicitly
-*   assume that R/O section consumes the first half 2 MB.
-*
-* In the long run, we should find and fix all those tools and scripts that
-* have incorrect implicit assumption of R/O section, but for now, we just
-* cannot squeeze the image size down to 2 MB at the risk of wrongly write-
-* protecting the R/W blobs.
-*/
-
 / {
 	flash@0 {
 		#address-cells = <1>;
@@ -39,13 +23,24 @@
 			"chromeos,flashmap";
 		reg = <0x00000000 0x00400000>;
 
+		/*
+		 * Note: rw-a and rw-b are used by auto-update. They must be
+		 * the same size, and must include the vblock, boot and
+		 * firmware-id parts within them. There is no check on this
+		 * at present so you need to manually verify that it is
+		 * correct.
+		 *
+		 * The rw-b section must not overlap/include the rw-vpd
+		 * section.
+		 */
+
 		/* ---- Section: Rewritable slot A ---- */
-		rw-a@200000 {
+		rw-a {
 			label = "rw-section-a";
 			/* Alignment: 4k (for updating) */
-			reg = <0x00200000 0x00078000>;
+			reg = <0x00200000 0x000f0000>;
 		};
-		rw-a-vblock@200000 {
+		rw-a-vblock {
 			label = "vblock-a";
 			/* Alignment: 4k (for updating) and must be in start of
 			 * each RW_SECTION. */
@@ -57,31 +52,31 @@
 			kernelkey = "kernel_subkey.vbpubk";
 			preamble-flags = <1>;
 		};
-		rw-a-boot@202000 {
+		rw-a-boot {
 			/* Alignment: no requirement (yet). */
 			label = "fw-main-a";
-			reg = <0x00202000 0x00075000>;
+			reg = <0x00202000 0x000edf00>;
 			type = "blob boot";
 		};
-		rw-a-firmware-id@277f00 {
+		rw-a-firmware-id {
 			/* Alignment: no requirement. */
 			label = "rw-fwid-a";
-			reg = <0x00277f00 0x00000100>;
+			reg = <0x002eff00 0x00000100>;
 			read-only;
 			type = "blobstring fwid";
 		};
 
 		/* ---- Section: Rewritable slot B ---- */
-		rw-b@278000 {
+		rw-b {
 			label = "rw-section-b";
 			/* Alignment: 4k (for updating) */
-			reg = <0x00278000 0x00078000>;
+			reg = <0x00300000 0x000f0000>;
 		};
-		rw-b-vblock@278000 {
+		rw-b-vblock {
 			label = "vblock-b";
 			/* Alignment: 4k (for updating) and must be in start of
 			 * each RW_SECTION. */
-			reg = <0x00278000 0x00002000>;
+			reg = <0x00300000 0x00002000>;
 			type = "keyblock boot";
 			keyblock = "firmware.keyblock";
 			signprivate = "firmware_data_key.vbprivk";
@@ -89,55 +84,55 @@
 			kernelkey = "kernel_subkey.vbpubk";
 			preamble-flags = <1>;
 		};
-		rw-b-boot@27a000 {
+		rw-b-boot {
 			label = "fw-main-b";
 			/* Alignment: no requirement (yet). */
-			reg = <0x0027a000 0x00075000>;
+			reg = <0x00302000 0x000edf00>;
 			type = "blob boot";
 		};
-		rw-b-firmware-id@2eff00 {
+		rw-b-firmware-id {
 			label = "rw-fwid-b";
 			/* Alignment: no requirement. */
-			reg = <0x002eff00 0x00000100>;
+			reg = <0x003eff00 0x00000100>;
 			read-only;
 			type = "blobstring fwid";
 		};
 
 		/* ---- Section: Rewritable VPD 32 KB ---- */
-		rw-vpd@2f0000 {
+		rw-vpd {
 			label = "rw-vpd";
 			/* Alignment: 4k (for updating) */
-			reg = <0x002f0000 0x00008000>;
+			reg = <0x003f0000 0x00008000>;
 			type = "wiped";
 			wipe-value = [ff];
 		};
 
 		/* ---- Section: Rewritable shared 16 KB---- */
-		shared-section@2f8000 {
+		shared-section {
 			/* Alignment: 4k (for updating).
 			 * Anything in this range may be updated in recovery. */
 			label = "rw-shared";
-			reg = <0x002f8000 0x00004000>;
+			reg = <0x003f8000 0x00004000>;
 		};
-		shared-data@2f8000 {
+		shared-data {
 			label = "shared-data";
 			/* Alignment: 4k (for random read/write).
 			 * RW firmware can put calibration data here. */
-			reg = <0x002f8000 0x00004000>;
+			reg = <0x003f8000 0x00004000>;
 			type = "wiped";
 			wipe-value = [00];
 		};
 		/* ---- Section: Rewritable private 16 KB---- */
-		private-section@2fc000 {
+		private-section {
 			/* Anything in this range will never be updated */
 			label = "rw-private";
-			reg = <0x002fc000 0x00004000>;
+			reg = <0x003fc000 0x00004000>;
 		};
-		dev-cfg@2fe000 {
+		dev-cfg {
 			label = "dev-cfg";
 			/* Alignment: 4k, and must occupy bottom of U-Boot
 			 * firmware -- check CONFIG_ENV_OFFSET */
-			reg = <0x002fe000 0x00002000>;
+			reg = <0x003fe000 0x00002000>;
 
 			/*
 			 * We could put the dev environment here, but U-Boot has