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authorSimon Glass <sjg@chromium.org>2011-08-22 08:08:29 -0600
committerSimon Glass <sjg@chromium.org>2011-09-15 12:56:44 -0700
commitce6431af149f778a465a34c7f283295637f478f9 (patch)
tree5d3821043c7b3790bbc7c7ff662a427ea38a2291 /board
parent7972cb1ca98af40ed9e79fb18d7170224ce70501 (diff)
fdt: Add Chrome OS memory areas
We want these to be fdt-controlled, rather than hard-coded with CONFIG settings. BUG=chromium-os:17062 TEST=build for Seaboard, mario Change-Id: Ic256b893559c5f722fe924315ab6a5755440c24c Reviewed-on: http://gerrit.chromium.org/gerrit/7641 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board')
-rw-r--r--board/chromebook-x86/coreboot/chromeos.dtsi5
-rw-r--r--board/nvidia/seaboard/chromeos.dtsi5
2 files changed, 10 insertions, 0 deletions
diff --git a/board/chromebook-x86/coreboot/chromeos.dtsi b/board/chromebook-x86/coreboot/chromeos.dtsi
index 0e0147b0687..c808354feeb 100644
--- a/board/chromebook-x86/coreboot/chromeos.dtsi
+++ b/board/chromebook-x86/coreboot/chromeos.dtsi
@@ -12,6 +12,11 @@
chromeos-config {
twostop; /* Two-stop boot */
twostop-optional; /* One-stop optimization enabled */
+
+ /* Memory addresses for kernel, cros-system and gbb */
+ kernel = <0x00100000 0x00800000>;
+ cros-system-data = <0x00900000 0x8000>;
+ google-binary-block = <0x00908000 0x80000>;
};
config {
diff --git a/board/nvidia/seaboard/chromeos.dtsi b/board/nvidia/seaboard/chromeos.dtsi
index c04ef8257b7..0088121556e 100644
--- a/board/nvidia/seaboard/chromeos.dtsi
+++ b/board/nvidia/seaboard/chromeos.dtsi
@@ -18,6 +18,11 @@
* Device and offset for second-stage firmware, in SPI for now
* second-stage = <&emmc 0x00000080 0>;
*/
+
+ /* Memory addresses for kernel, cros-system and gbb */
+ kernel = <0x00100000 0x00800000>;
+ cros-system-data = <0x00900000 0x8000>;
+ google-binary-block = <0x00908000 0x80000>;
};
config {