diff options
| author | Justin Waters <justin.waters@timesys.com> | 2008-06-16 13:31:33 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2008-06-16 13:31:33 -0400 |
| commit | 251484cfb845d5d54c652a1801270ede1521ca6d (patch) | |
| tree | d89611f0f7d9f1cd468c53d2cb122041db75b74a /board | |
| parent | fc0717dc30824a3e0b9115c44787af7483e5aaa7 (diff) | |
Update to Atmel's 1.7 patch for 1.1.51.1.5-at91-200806161731
This patch came from Atmel. It fixes a number of NAND issues, as well as the
9263 rev B SPI bug.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/at91sam9260ek/nand.c | 20 | ||||
| -rw-r--r-- | board/at91sam9rlek/nand.c | 10 |
2 files changed, 23 insertions, 7 deletions
diff --git a/board/at91sam9260ek/nand.c b/board/at91sam9260ek/nand.c index 2a339a9ed7..53da6fd108 100644 --- a/board/at91sam9260ek/nand.c +++ b/board/at91sam9260ek/nand.c @@ -52,7 +52,7 @@ void at91sam9260ek_nand_init (struct nand_chip *nand) if ((nand->options & NAND_BUSWIDTH_16) == NAND_BUSWIDTH_16) { - AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF); } else { AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | @@ -65,8 +65,9 @@ void at91sam9260ek_nand_init (struct nand_chip *nand) AT91C_BASE_PIOC->PIO_ODR = AT91C_PIO_PC13; AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC13; - AT91C_BASE_PIOC->PIO_PPUER = AT91C_PIO_PC13; /* Enable pull-up */ - + /* Enable pull-up */ + AT91C_BASE_PIOC->PIO_PPUER = AT91C_PIO_PC13; + /* Enable NandFlash */ AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC14; AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC14; @@ -97,6 +98,19 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd) void board_nand_init(struct nand_chip *nand) { + /* Init due to switch 8/16 bits mode */ + + if (nand->write_byte) + nand->write_byte = NULL; + if (nand->read_byte) + nand->read_byte = NULL; + if (nand->write_buf) + nand->write_buf = NULL; + if (nand->read_buf) + nand->read_buf = NULL; + if (nand->verify_buf) + nand->verify_buf = NULL; + nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = at91sam9260ek_nand_hwcontrol; nand->dev_ready = at91sam9260ek_nand_ready; diff --git a/board/at91sam9rlek/nand.c b/board/at91sam9rlek/nand.c index 62623f5fbe..60973458ab 100644 --- a/board/at91sam9rlek/nand.c +++ b/board/at91sam9rlek/nand.c @@ -53,12 +53,14 @@ void at91sam9RLek_nand_init (struct nand_chip *nand) AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF); - /* Clock PIOD */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD; + /* Clock PIOD & PIOB */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOD); + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Configure Ready/Busy signal */ AT91C_BASE_PIOD->PIO_ODR = AT91C_PIO_PD17; AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD17; + /* Configure pull-up */ AT91C_BASE_PIOD->PIO_PPUER = AT91C_PIO_PD17; @@ -80,8 +82,8 @@ static void at91sam9RLek_nand_hwcontrol(struct mtd_info *mtd, int cmd) switch (cmd) { case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; - case NAND_CTL_CLRNCE: *AT91C_PIOC_SODR = AT91C_PIO_PC14; break; - case NAND_CTL_SETNCE: *AT91C_PIOC_CODR = AT91C_PIO_PC14; break; + case NAND_CTL_CLRNCE: *AT91C_PIOB_SODR = AT91C_PIO_PB6; break; + case NAND_CTL_SETNCE: *AT91C_PIOB_CODR = AT91C_PIO_PB6; break; } this->IO_ADDR_W = (void *) IO_ADDR_W; } |