diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2015-04-22 15:43:40 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2015-04-22 15:43:40 +0200 |
| commit | 0440936084e5f467b55f56d7d1fa8660732587bd (patch) | |
| tree | 1e73ad40d820f1829c1bfd5ff3b91e71105f14de /board | |
| parent | 226245bd56adc631d9a1d0c1297e78d819ea478f (diff) | |
video: dcu: enable pixel clock after initialization
When enabling the DCU and pixel clock, the test mode is activated
since this is the reset configuration. The test mode immediately
shows a red screen on a LCD. A moment later, the DCU gets
initialized properly.
This patch enables the pixel clock after initialization of the DCU
control register. This avoids this initial flicker on LCD screens.
Diffstat (limited to 'board')
| -rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 5 | ||||
| -rw-r--r-- | board/toradex/colibri_vf/dcu.c | 6 |
2 files changed, 6 insertions, 5 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index d9cc5fae5e..aef8511aa9 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -328,11 +328,6 @@ static void clock_init(void) setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); - - clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL); - clrsetbits_le32(&ccm->cscdr3, - CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN, - CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN); #endif } diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c index 861b95c948..3c01213a12 100644 --- a/board/toradex/colibri_vf/dcu.c +++ b/board/toradex/colibri_vf/dcu.c @@ -6,6 +6,7 @@ */ #include <asm/arch/crm_regs.h> +#include <asm/io.h> #include <common.h> #include <fsl_dcu_fb.h> #include "div64.h" @@ -14,8 +15,13 @@ DECLARE_GLOBAL_DATA_PTR; unsigned int dcu_set_pixel_clock(unsigned int pixclock) { + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; unsigned long long div; + clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL); + clrsetbits_le32(&ccm->cscdr3, + CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN, + CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN); div = (unsigned long long)(PLL1_PFD2_FREQ / 1000); do_div(div, pixclock); |