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authorEgli, Samuel <samuel.egli@siemens.com>2015-12-02 15:27:56 +0100
committerTom Rini <trini@konsulko.com>2015-12-12 15:56:09 -0500
commit69b918b65d11d030ff39dcc9b5f4d4605cd23c7f (patch)
treece64508f6a2a3ff19226366c52b41875f442455c /board
parentb3b522f247d3f19c4f2309ab0e6a02b3dd82de45 (diff)
am33xx,ddr3: fix ddr3 sdram configuration
This patch fixes the DDR3 initialization procedure in order to comply with DDR3 standard. A 500 us delay is specified between the DDR3 reset and clock enable signal. Until now, this delay was not respected. Some DDR3 chips don't bother but the bigger the RAM becomes the more likely it seems that this delay is needed. We observed that DRAM > 256 MB from the manufacturer Samsung have an issue when the specification is not respected. Changes: 1) Add a 1 ms wait for L3 timeout error trigger 2) Don't delay DDR3 initialization Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his suppresses the initialization of DDR3 Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
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