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authorTom Rini <trini@konsulko.com>2016-04-13 12:53:11 -0400
committerTom Rini <trini@konsulko.com>2016-04-13 12:53:11 -0400
commit541c9be880d601cb0230dc7452c398167ed1eaac (patch)
tree0686261e2d2e4589c651d165026d4e678390915a /board
parent3f8085e94ae3e8a2996e2f517ecdb608a4b4c09e (diff)
parent58ed7f66939cbfb6e48656b3925aefd9f180a1a3 (diff)
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'board')
-rw-r--r--board/xilinx/zynq/board.c132
-rw-r--r--board/xilinx/zynqmp/zynqmp.c7
2 files changed, 123 insertions, 16 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4c20450b63..183f642753 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
return 0;
}
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+ const u32 *cell, int n)
+{
+ int i = 0, b, banks;
+ int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+ int address_cells = fdt_address_cells(fdt, parent_offset);
+ int size_cells = fdt_size_cells(fdt, parent_offset);
+ char *p = buf;
+ u64 val;
+ u64 vals;
+
+ debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+ __func__, address_cells, size_cells, buf, cell);
+
+ /* Check memory bank setup */
+ banks = n % (address_cells + size_cells);
+ if (banks)
+ panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+ n, address_cells, size_cells);
+
+ banks = n / (address_cells + size_cells);
+
+ for (b = 0; b < banks; b++) {
+ debug("%s: Bank #%d:\n", __func__, b);
+ if (address_cells == 2) {
+ val = cell[i + 1];
+ val <<= 32;
+ val |= cell[i];
+ val = fdt64_to_cpu(val);
+ debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+ __func__, val, p, &cell[i]);
+ *(phys_addr_t *)p = val;
+ } else {
+ debug("%s: addr32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_addr_t);
+ i += address_cells;
+
+ debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+ sizeof(phys_addr_t));
+
+ if (size_cells == 2) {
+ vals = cell[i + 1];
+ vals <<= 32;
+ vals |= cell[i];
+ vals = fdt64_to_cpu(vals);
+
+ debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+ __func__, vals, p, &cell[i]);
+ *(phys_size_t *)p = vals;
+ } else {
+ debug("%s: size32=%x, ptr=%p\n",
+ __func__, fdt32_to_cpu(cell[i]), p);
+ *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+ }
+ p += sizeof(phys_size_t);
+ i += size_cells;
+
+ debug("%s: ps=%p, i=%x, size=%zu\n",
+ __func__, p, i, sizeof(phys_size_t));
+ }
+
+ /* Return the first address size */
+ return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+ int bank;
+
+ memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ debug("Bank #%d: start %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start);
+ debug("Bank #%d: size %llx\n", bank,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+ }
+}
+
int dram_init(void)
{
- int node;
- fdt_addr_t addr;
- fdt_size_t size;
+ int node, len;
const void *blob = gd->fdt_blob;
+ const u32 *cell;
- node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
- "memory", 7);
- if (node == -FDT_ERR_NOTFOUND) {
- debug("ZYNQ DRAM: Can't get memory node\n");
- return -1;
+ memset(&tmp, 0, sizeof(tmp));
+
+ /* find or create "/memory" node. */
+ node = fdt_subnode_offset(blob, 0, "memory");
+ if (node < 0) {
+ printf("%s: Can't get memory node\n", __func__);
+ return node;
}
- addr = fdtdec_get_addr_size(blob, node, "reg", &size);
- if (addr == FDT_ADDR_T_NONE || size == 0) {
- debug("ZYNQ DRAM: Can't get base address or size\n");
+
+ /* Get pointer to cells and lenght of it */
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell) {
+ printf("%s: Can't get reg property\n", __func__);
return -1;
}
- gd->ram_size = size;
+
+ gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+ debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+ zynq_ddrc_init();
+
+ return 0;
+}
+#else
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
zynq_ddrc_init();
return 0;
}
+#endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 087578cb6b..132d724fbd 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -6,7 +6,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
@@ -63,8 +62,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
int address_cells = fdt_address_cells(fdt, parent_offset);
int size_cells = fdt_size_cells(fdt, parent_offset);
char *p = buf;
- phys_addr_t val;
- phys_size_t vals;
+ u64 val;
+ u64 vals;
debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
__func__, address_cells, size_cells, buf, cell);
@@ -166,7 +165,7 @@ int dram_init(void)
gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
- debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+ debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
return 0;
}