diff options
| author | Jerry Huang <Chang-Ming.Huang@freescale.com> | 2010-01-25 14:33:29 +0800 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-29 17:32:29 -0400 |
| commit | a6060fb63152c705b3a2b1355ce0840ce4afd1dc (patch) | |
| tree | f45b9ab1185637a8f328fbd228f604bf56c79db4 /board | |
| parent | 9e2ee7c62e1f7596ad01432063396664f7af0b75 (diff) | |
p1022ds: On-Chip ROM boot support
Including boot from eSDHC and eSPI.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/p1022ds/config.mk | 12 | ||||
| -rw-r--r-- | board/freescale/p1022ds/p1022ds.c | 4 | ||||
| -rw-r--r-- | board/freescale/p1022ds/tlb.c | 15 |
3 files changed, 27 insertions, 4 deletions
diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk index be0cb2c48b..75f4e37841 100644 --- a/board/freescale/p1022ds/config.mk +++ b/board/freescale/p1022ds/config.mk @@ -23,8 +23,20 @@ # # p1022ds board # +ifeq ($(CONFIG_MK_SDCARD), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0x1107fffc +endif + +ifeq ($(CONFIG_MK_SPIFLASH), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0x1107fffc +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffffffc +endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 39c441009e..4b2e1345de 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -98,6 +98,10 @@ phys_size_t initdram(int board_type) puts("Initializing...."); +#if defined(CONFIG_SYS_RAMBOOT) + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif + #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); #else diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index fac7ebbf09..e5eb93a5d2 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -82,10 +82,17 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), - /* *I*G - NAND */ -/* SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, */ -/* MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, */ -/* 0, 7, BOOKE_PAGESZ_1M, 1), */ +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC/eSPI/NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |