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authorwdenk <wdenk>2003-06-22 17:18:28 +0000
committerwdenk <wdenk>2003-06-22 17:18:28 +0000
commit3595ac4979e648e102c7a500e3c63193a27953bc (patch)
treeb15884457b571ad55691fa8a0a6841d5dde15a14 /board
parent9a0e21a3a87830f66a93c17d1bca66fd12d860ae (diff)
* Patch by Rune Torgersen, 4 Jun 2003:
add large memory support for MPC8266ADS board * Patch by Richard Woodruff, 19 June 03: - Enabled standard u-boot device abstraction for ARM - Enabled console device for ARM - Initilized bi_baudrate for ARM * Patch by Bill Hargen, 23 Apr 2003: fix byte order for 824x I2C addresses (write op)
Diffstat (limited to 'board')
-rw-r--r--board/mpc8266ads/mpc8266ads.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c
index 501e610d599..c6c8d761cb5 100644
--- a/board/mpc8266ads/mpc8266ads.c
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -46,7 +46,7 @@
* PSDMR_BUFCMD adds a clock
* 0 no extra clock
*/
-#define CONFIG_PBI 0
+#define CONFIG_PBI PSDMR_PBI
#define PESSIMISTIC_SDRAM 0
#define EAMUX 0 /* EST requires EAMUX */
#define BUFCMD 0
@@ -379,6 +379,25 @@ long int initdram(int board_type)
sdram_size = 1 << (rows + cols + banks + width);
+ /* hack for high density memory (512MB per CS) */
+ /* !!!!! Will ONLY work with Page Based Interleave !!!!!
+ ( PSDMR[PBI] = 1 )
+ */
+ /* mamory actually has 11 column addresses, but the memory controller
+ doesn't really care.
+ the calculations that follow will however move the rows so that
+ they are muxed one bit off if you use 11 bit columns.
+ The solution is to tell the memory controller the correct size of the memory
+ but change the number of columns to 10 afterwards.
+ The 11th column addre will still be mucxed correctly onto the bus.
+
+ Also be aware that the MPC8266ADS board Rev B has not connected
+ Row addres 13 to anything.
+
+ The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
+ */
+ if (cols > 10)
+ cols = 10;
#if(CONFIG_PBI == 0) /* bank-based interleaving */
rowst = ((32 - 6) - (rows + cols + width)) * 2;