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authorChris Packham <judge.packham@gmail.com>2018-05-10 13:28:30 +1200
committerStefan Roese <sr@denx.de>2018-05-14 10:01:56 +0200
commite6f61622d32327907f824154c7f88ddce3c700cc (patch)
treeda08a5e3e1811a0fda31e4a4e64e37f3318d947d /board
parent2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a (diff)
ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the ddr_topology. This was originally implemented in commit 90bcc3d38d2b ("driver/ddr: Add support for setting timing in hws_topology_map") but was removed as part of the upstream sync. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
-rw-r--r--board/CZ.NIC/turris_omnia/turris_omnia.c6
-rw-r--r--board/Marvell/db-88f6820-amc/db-88f6820-amc.c3
-rw-r--r--board/Marvell/db-88f6820-gp/db-88f6820-gp.c3
-rw-r--r--board/gdsys/a38x/controlcenterdc.c3
-rw-r--r--board/solidrun/clearfog/clearfog.c3
5 files changed, 12 insertions, 6 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 29f81cdccfd..da663cf1bb0 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -214,7 +214,8 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_NORMAL} }, /* temperature */
+ MV_DDR_TEMP_NORMAL, /* temperature */
+ MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
@@ -235,7 +236,8 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
MV_DDR_DIE_CAP_8GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_NORMAL} }, /* temperature */
+ MV_DDR_TEMP_NORMAL, /* temperature */
+ MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index e39dc75f922..92d7ae77f07 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -69,7 +69,8 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_DIE_CAP_2GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW} }, /* temperature */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index ee12ca68ec2..a8cfe8af0a8 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -90,7 +90,8 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW} }, /* temperature */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index f750e47b722..320bc100c9d 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -53,7 +53,8 @@ static struct mv_ddr_topology_map ddr_topology_map = {
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_533, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW} }, /* temperature */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index cc11feb85e3..ede303d4ebf 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -83,7 +83,8 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW} }, /* temperature */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */