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authorWolfgang Denk <wd@denx.de>2008-04-08 00:10:17 +0200
committerWolfgang Denk <wd@denx.de>2008-04-08 00:10:17 +0200
commit2c78febd114b716714e7ac83c17bac5e30066512 (patch)
tree2fc53ae7781aca121aefa5e21796eee0c94f5611 /board
parent34e6cb8d1d9dc8194b2d8cad1cc39273ac58f8d8 (diff)
parent9b46432fc65ce0f0826b32e4f15c15b33ccb8d42 (diff)
Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire
Diffstat (limited to 'board')
-rw-r--r--board/freescale/m5275evb/Makefile (renamed from board/r5200/Makefile)20
-rw-r--r--board/freescale/m5275evb/config.mk (renamed from board/r5200/config.mk)2
-rw-r--r--board/freescale/m5275evb/m5275evb.c112
-rw-r--r--board/freescale/m5275evb/mii.c (renamed from board/r5200/mii.c)22
-rw-r--r--board/freescale/m5275evb/u-boot.lds (renamed from board/r5200/u-boot.lds)41
-rw-r--r--board/freescale/m54455evb/flash.c449
-rw-r--r--board/freescale/m547xevb/m547xevb.c3
-rw-r--r--board/r5200/r5200.c124
8 files changed, 543 insertions, 230 deletions
diff --git a/board/r5200/Makefile b/board/freescale/m5275evb/Makefile
index 2ec71ee1d27..9a0fa805387 100644
--- a/board/r5200/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,22 +23,18 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+OBJS = $(BOARD).o mii.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
#########################################################################
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-sinclude $(obj).depend
+sinclude .depend
#########################################################################
diff --git a/board/r5200/config.mk b/board/freescale/m5275evb/config.mk
index 8fc5319798d..ccb2cf735df 100644
--- a/board/r5200/config.mk
+++ b/board/freescale/m5275evb/config.mk
@@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0x10000000
+TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 00000000000..a1b2902935f
--- /dev/null
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+#define PERIOD 13 /* system bus period in ns */
+#define SDRAM_TREFI 7800 /* in ns */
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5275 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+ gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+
+ /* Set up chip select */
+ sdp->sdbar0 = CFG_SDRAM_BASE;
+ sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+
+ /* Set up timing */
+ sdp->sdcfg1 = 0x83711630;
+ sdp->sdcfg2 = 0x46770000;
+
+ /* Enable clock */
+ sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LEMR */
+ sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
+ | MCF_SDRAMC_SDMR_AD(0x0)
+ | MCF_SDRAMC_SDMR_CMD;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LMR */
+ sdp->sdmr = 0x058d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop manual precharge, send 2 IREF */
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Write mode register, clear reset DLL */
+ sdp->sdmr = 0x018d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+
+ /* Turn on auto refresh, lock SDMR */
+ sdp->sdcr =
+ MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_MUX(1)
+ /* 1 added to round up */
+ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/r5200/mii.c b/board/freescale/m5275evb/mii.c
index 706c90f6435..bbc93f6d483 100644
--- a/board/r5200/mii.c
+++ b/board/freescale/m5275evb/mii.c
@@ -36,10 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
int fecpin_setclear(struct eth_device *dev, int setclear)
{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
} else {
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
}
return 0;
@@ -131,7 +147,7 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
@@ -200,7 +216,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
diff --git a/board/r5200/u-boot.lds b/board/freescale/m5275evb/u-boot.lds
index 29fe58941b4..43d65001b39 100644
--- a/board/r5200/u-boot.lds
+++ b/board/freescale/m5275evb/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -33,37 +33,36 @@ SECTIONS
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
+ lib_generic/string.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ common/environment.o(.text)
*(.text)
*(.fixup)
@@ -84,8 +83,7 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
-
- .reloc :
+ .reloc :
{
__got_start = .;
*(.got)
@@ -115,7 +113,6 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
@@ -129,7 +126,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
- .bss (NOLOAD) :
+ .bss :
{
_sbss = .;
*(.sbss) *(.scommon)
diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c
index de2cca863a9..6b50e8d8290 100644
--- a/board/freescale/m54455evb/flash.c
+++ b/board/freescale/m54455evb/flash.c
@@ -95,6 +95,11 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+#define STM_ID_M25P16 0x20152015
+#define FLASH_M25P16 0x0055
+#endif
+
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
@@ -111,6 +116,12 @@ void inline spin_wheel(void);
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
+int serial_flash_read_status(int chipsel);
+static int ser_flash_cs = 0;
+#endif
+
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
@@ -119,6 +130,10 @@ ulong flash_init(void)
ulong size = 0;
ulong fbase = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ dspi_init();
+#endif
+
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
@@ -129,6 +144,11 @@ ulong flash_init(void)
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 2:
+ fbase = (ulong) CFG_FLASH2_BASE;
+ break;
+#endif
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
@@ -152,7 +172,6 @@ int flash_get_offsets(ulong base, flash_info_t * info)
{
int i, j, k;
int sectors, bs, banks;
- ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
@@ -196,6 +215,15 @@ int flash_get_offsets(ulong base, flash_info_t * info)
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+ info->start[0] = CFG_FLASH2_BASE;
+ for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
+ info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
+ info->protect[k] = 0;
+ }
+ }
+#endif
return ERR_OK;
}
@@ -211,6 +239,11 @@ void flash_print_info(flash_info_t * info)
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ printf("ST ");
+ break;
+#endif
default:
printf("Unknown Vendor ");
break;
@@ -221,8 +254,13 @@ void flash_print_info(flash_info_t * info)
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
- printf("Intel 28F128J3A\n");
+ printf("28F128J3A\n");
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_M25P16:
+ printf("M25P16\n");
break;
+#endif
default:
printf("Unknown Chip Type\n");
return;
@@ -267,6 +305,45 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info)
u16 value;
int i;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((ulong) addr == CFG_FLASH2_BASE) {
+ int manufactId = 0;
+ int deviceId = 0;
+
+ ser_flash_cs = 1;
+
+ dspi_tx(ser_flash_cs, 0x80, SER_RDID);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+
+ dspi_rx();
+ manufactId = dspi_rx();
+ deviceId = dspi_rx() << 8;
+ deviceId |= dspi_rx();
+
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ switch (manufactId) {
+ case (u8) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ }
+
+ switch (deviceId) {
+ case (u16) STM_ID_M25P16:
+ info->flash_id += FLASH_M25P16;
+ break;
+ }
+
+ info->sector_count = CFG_STM_SECT;
+ info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
+
+ return (info->size);
+ }
+#endif
+
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
@@ -383,6 +460,21 @@ int flash_cmd_rd(volatile u16 * addr, int index)
return (int)addr[index];
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int serial_flash_read_status(int chipsel)
+{
+ u16 status;
+
+ dspi_tx(chipsel, 0x80, SER_RDSR);
+ dspi_rx();
+
+ dspi_tx(chipsel, 0x00, 0);
+ status = dspi_rx();
+
+ return status;
+}
+#endif
+
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
@@ -462,8 +554,11 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
- int rcode = 0, intel = 0;
-
+ int rcode = 0, flashtype = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ int count;
+ u16 status;
+#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
@@ -474,19 +569,25 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
type = (info->flash_id & FLASH_VENDMASK);
- if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
- if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
- type = (info->flash_id & FLASH_VENDMASK);
- printf
- ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
+ switch (type) {
+ case FLASH_MAN_ATM:
+ flashtype = 1;
+ break;
+ case FLASH_MAN_INTEL:
+ flashtype = 2;
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ flashtype = 3;
+ break;
+#endif
+ default:
+ type = (info->flash_id & FLASH_VENDMASK);
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
}
- if (type == FLASH_MAN_INTEL)
- intel = 1;
-
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
@@ -503,6 +604,51 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
start = get_timer(0);
last = start;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ /* Perform bulk erase */
+ if (flashtype == 3) {
+ if ((s_last - s_first) == (CFG_STM_SECT - 1)) {
+ if (prot == 0) {
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Can't erase flash\n");
+ return 1;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE);
+ dspi_rx();
+
+ count = 0;
+ start = get_timer(0);
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (count++ > 0x10000) {
+ spin_wheel();
+ count = 0;
+ }
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ printf("\b. done\n");
+ return 0;
+ } else if (prot == CFG_STM_SECT) {
+ return 1;
+ }
+ }
+ }
+#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
@@ -515,65 +661,116 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
- if (intel) {
- *addr = (FPW) INTEL_READID;
- min = addr[INTEL_CFI_TERB] & 0xff;
- min = 1 << min; /* ms */
- min = (min / info->sector_count) * 1000;
-
- /* start erase block */
- *addr = (FPW) INTEL_CLEAR; /* clear status register */
- *addr = (FPW) INTEL_ERASE; /* erase setup */
- *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
-
- while ((*addr & (FPW) INTEL_FINISHED) !=
- (FPW) INTEL_FINISHED) {
-
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
- *addr = (FPW) INTEL_RESET; /* reset to read mode */
-
- rcode = 1;
- break;
+ switch (flashtype) {
+ case 1:
+ {
+ FPWV *base; /* first address in bank */
+ FPWV *atmeladdr;
+
+ flag = disable_interrupts();
+
+ atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
+ base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ *atmeladdr = (u8) 0x00300030; /* erase sector */
+
+ if (flag)
+ enable_interrupts();
+
+ while ((*atmeladdr & (u8) 0x00800080) !=
+ (u8) 0x00800080) {
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
}
- }
-
- *addr = (FPW) INTEL_RESET; /* resest to read mode */
- } else {
- FPWV *base; /* first address in bank */
- FPWV *atmeladdr;
-
- flag = disable_interrupts();
- atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
- base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
-
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- *atmeladdr = (u8) 0x00300030; /* erase sector */
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ break;
+ }
- if (flag)
- enable_interrupts();
+ case 2:
+ {
+ *addr = (FPW) INTEL_READID;
+ min = addr[INTEL_CFI_TERB] & 0xff;
+ min = 1 << min; /* ms */
+ min = (min / info->sector_count) * 1000;
+
+ /* start erase block */
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+ while ((*addr & (FPW) INTEL_FINISHED) !=
+ (FPW) INTEL_FINISHED) {
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
+ *addr = (FPW) INTEL_RESET; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
- while ((*atmeladdr & (u8) 0x00800080) !=
- (u8) 0x00800080) {
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ *addr = (FPW) INTEL_RESET; /* resest to read mode */
+ break;
+ }
- rcode = 1;
- break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 3:
+ {
+ u8 sec = ((ulong) addr >> 16) & 0xFF;
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
}
- }
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
- } /* Atmel or Intel */
+ dspi_tx(ser_flash_cs, 0x80,
+ SER_SECT_ERASE);
+ dspi_tx(ser_flash_cs, 0x80, sec);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x00, 0);
+
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ break;
+ }
+#endif
+ } /* switch (flashtype) */
}
}
printf(" done\n");
@@ -583,6 +780,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
+ int count;
+
if (info->flash_id == FLASH_UNKNOWN)
return 4;
@@ -623,7 +822,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
u16 data;
- int count, i, l, rc, port_width;
+ int i, l, rc, port_width;
/* get lower word aligned address */
wp = addr;
@@ -724,6 +923,51 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
} /* case FLASH_MAN_INTEL */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ {
+ ulong wp;
+ u8 *data = (u8 *) src;
+ int left; /* number of bytes left to program */
+
+ wp = addr;
+
+ /* page align, each page is 256 bytes */
+ if ((wp % 0x100) != 0) {
+ left = (0x100 - (wp & 0xFF));
+ write_ser_data(info, wp, data, left);
+ cnt -= left;
+ wp += left;
+ data += left;
+ }
+
+ /* page program - 256 bytes at a time */
+ if (cnt > 255) {
+ count = 0;
+ while (cnt >= 0x100) {
+ write_ser_data(info, wp, data, 0x100);
+ cnt -= 0x100;
+ wp += 0x100;
+ data += 0x100;
+
+ if (count++ > 0x400) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ }
+
+ /* remainint bytes */
+ if (cnt && (cnt < 256)) {
+ write_ser_data(info, wp, data, cnt);
+ wp += cnt;
+ data += cnt;
+ cnt -= cnt;
+ }
+
+ printf("\b.");
+ }
+#endif
} /* switch */
return ERR_OK;
@@ -844,6 +1088,75 @@ int write_data(flash_info_t * info, ulong dest, FPW data)
return (0);
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt)
+{
+ ulong start;
+ int status, i;
+ u8 flashdata;
+
+ /* Check if Flash is (sufficiently) erased */
+ dspi_tx(ser_flash_cs, 0x80, SER_READ);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, dest & 0xFF);
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ flashdata = dspi_rx();
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ if ((flashdata & *data) != *data) {
+ printf("not erased at %08lx (%lx)\n", (ulong) dest,
+ (ulong) flashdata);
+ return (2);
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
+ }
+
+ start = get_timer(0);
+
+ dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG);
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16));
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8));
+ dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF));
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ for (i = 0; i < (cnt - 1); i++) {
+ dspi_tx(ser_flash_cs, 0x80, *data);
+ dspi_rx();
+ data++;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, *data);
+ dspi_rx();
+
+ do {
+ status = serial_flash_read_status(ser_flash_cs);
+
+ if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ return (0);
+}
+#endif
+
/*-----------------------------------------------------------------------
* Write a word to Flash for ATMEL FLASH
* A word is 16 bits, whichever the bus width of the flash bank
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 0286084a8ee..539da78de98 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -43,6 +43,9 @@ long int initdram(int board_type)
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
+#ifdef CFG_DRAMSZ1
+ u32 temp;
+#endif
siu->drv = CFG_SDRAM_DRVSTRENGTH;
diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c
deleted file mode 100644
index 69f3a765b61..00000000000
--- a/board/r5200/r5200.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-
-
-int checkboard (void) {
- puts ("Board: R5200 Ethernet Module\n");
- return 0;
-};
-
-long int initdram (int board_type) {
- int i;
-
- /*
- * Set CS2 pin to be SD_CS0
- */
- mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
- | MCF_GPIO_PAR_CS_PAR_CS2);
-
- mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
- | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
- /*
- * Initialize DRAM Control Register: DCR
- */
- mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
- | MCF_SDRAMC_DCR_RC(0x30));
-
- /*
- * Initialize DACR0
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
- | MCF_SDRAMC_DACRn_CASL(0)
- | MCF_SDRAMC_DACRn_CBM(3)
- | MCF_SDRAMC_DACRn_PS(2));
-
- /*
- * Initialize DMR0
- */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_8M
- | MCF_SDRAMC_DMRn_V);
-
- /*
- * Set IP bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_IP);
-
- /*
- * Wait at least 20ns to allow banks to precharge
- */
- for (i = 0; i < 5; i++)
- asm(" nop");
-
- /*
- * Write to this block to initiate precharge
- */
- *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
-
- /*
- * Set RE bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_RE);
-
-
- /*
- * Wait for at least 8 auto refresh cycles to occur
- */
- for (i = 0; i < 2000; i++)
- asm(" nop");
-
- /*
- * Finish the configuration by issuing the MRS.
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_MRS);
-
-
- /*
- * Write to the SDRAM Mode Register
- */
- *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
- }
-
- return CFG_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}