diff options
| author | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-06-01 10:01:49 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-08-11 18:46:07 +0800 |
| commit | f4512618caa0182344aa55c5e15b2a14e28227cd (patch) | |
| tree | 1f8782d42c0530bff0d7df64aa22f62fd6c831c2 /board | |
| parent | a5041e33e4f05efec8a412641243c9281cba47e9 (diff) | |
riscv: ae350: Fix XIP config boot failure
The booting flow is SPL -> OpenSBI -> U-Boot.
The boot hart may change after OpenSBI and may not always be hart0,
so wrap the related branch instruction with M-MODE.
Current DTB setup for XIP is not valid.
There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used
in XIP mode, to be returned. Fix this.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/AndesTech/ax25-ae350/ax25-ae350.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index d6a4291379..36f0dd4b0f 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -54,17 +54,22 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) return 0; } +#define ANDES_HW_DTB_ADDRESS 0xF2000000 void *board_fdt_blob_setup(int *err) { *err = 0; -#if defined(CONFIG_OF_BOARD) - return (void *)(ulong)gd->arch.firmware_fdt_addr; -#elif defined(CONFIG_OF_SEPARATE) - return (void *)CONFIG_SYS_FDT_BASE; -#else + + if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { + if (gd->arch.firmware_fdt_addr) + return (void *)(ulong)gd->arch.firmware_fdt_addr; + } + + if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) + return (void *)CONFIG_SYS_FDT_BASE; + return (void *)ANDES_HW_DTB_ADDRESS; + *err = -EINVAL; return NULL; -#endif } int smc_init(void) |