diff options
| author | Jason Liu <r64343@freescale.com> | 2012-04-17 11:06:52 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2012-09-12 11:05:48 -0400 |
| commit | c69212bce7f9f65e6b0411b84e807cec39dad44d (patch) | |
| tree | 32b5144332fbd101e7d23476c41eff3f4a53557a /board | |
| parent | d032ced64b67b7856d4e5ed281d0487e07381599 (diff) | |
ENGR00179762: i.MX6: print the SOC revision correctly
For example: The soc rev on i.mx6dl rev 1.0 not print correctly:
CPU: Freescale i.MX 6 family 0.0V at 792 MHz
This patch help u-boot print out the SOC revision correctly:
CPU: Freescale i.MX6 family TO1.0 at 792 MHz
Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/common/fsl_sys_rev.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/board/freescale/common/fsl_sys_rev.c b/board/freescale/common/fsl_sys_rev.c index 26f9f1786b..ba4c367d42 100644 --- a/board/freescale/common/fsl_sys_rev.c +++ b/board/freescale/common/fsl_sys_rev.c @@ -63,13 +63,20 @@ void fsl_set_system_rev(void) * i.MX6Q1.0: 6300 00 * i.MX6Q1.1: 6300 01 * i.MX6Solo1.0: 6100 00 + + * Thus the system_rev will be the following layout: + * | 31 - 20 | 19 - 12 | 11 - 8 | 7 - 0 | + * | resverd | CHIP ID | BD REV | SI REV | */ u32 cpu_type = readl(ANATOP_BASE_ADDR + 0x260); u32 board_type = 0; /* Chip Silicon ID */ - fsl_system_rev = (cpu_type >> 4) & 0xFF000; - /* Chip Revision ID */ - fsl_system_rev |= (cpu_type & 0xFF); + fsl_system_rev = ((cpu_type >> 16) & 0xFF) << 12; + /* Chip silicon major revision */ + fsl_system_rev |= ((cpu_type >> 8) & 0xFF) << 4; + fsl_system_rev += 0x10; + /* Chip silicon minor revision */ + fsl_system_rev |= cpu_type & 0xFF; /* Get Board ID information from OCOTP_GP1[15:8] * bit 12-15: Board type |