diff options
| author | Simon Glass <sjg@chromium.org> | 2011-04-28 10:06:17 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-24 09:54:52 -0700 |
| commit | 696ba76e40fefcc58848b5e86575915927840c6a (patch) | |
| tree | 62f058fc347bcee53b1b9072be0d1f1206e7818b /board | |
| parent | 1640039ca2f8a4b9ca04106295cc8dfd6c97a82e (diff) | |
Tegra2: Use clock and pinmux functions to simplify code
BUG=chromium-os:13875
TEST=Build for Seaboard, boot
Review URL: http://codereview.chromium.org/6899017
Change-Id: I6bb151ff353dba2192ab56a9db9ac9628133ec4e
Diffstat (limited to 'board')
| -rw-r--r-- | board/nvidia/common/board.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index f07328ebb97..ac2e3f87dbb 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -24,6 +24,7 @@ #include <common.h> #include <ns16550.h> #include <asm/io.h> +#include <asm/arch/bitfield.h> #include <asm/arch/tegra2.h> #include <asm/arch/sys_proto.h> @@ -78,20 +79,20 @@ static void clock_init_uart(void) u32 reg; reg = readl(&pll->pll_base); - if (!(reg & PLL_BASE_OVRRIDE_BIT)) { + if (!(reg & bf_mask(PLL_BASE_OVRRIDE))) { /* Override pllp setup for 216MHz operation. */ - reg = (PLL_BYPASS_BIT | PLL_BASE_OVRRIDE_BIT | PLL_DIVP_VALUE); - reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE); + reg = bf_mask(PLL_BYPASS) | bf_mask(PLL_BASE_OVRRIDE) | + bf_pack(PLL_DIVP, 1) | bf_pack(PLL_DIVM, 0xc); + reg |= bf_pack(PLL_DIVN, NVRM_PLLP_FIXED_FREQ_KHZ / 500); writel(reg, &pll->pll_base); - reg |= PLL_ENABLE_BIT; + reg |= bf_mask(PLL_ENABLE); writel(reg, &pll->pll_base); - reg &= ~PLL_BYPASS_BIT; + reg &= ~bf_mask(PLL_BYPASS); writel(reg, &pll->pll_base); } - /* Now do the UART reset/clock enable */ #if defined(CONFIG_TEGRA2_ENABLE_UARTA) /* Assert UART reset and enable clock */ reset_set_enable(PERIPH_ID_UART1, 1); |