diff options
| author | Sandeep Gopalpet <sandeep.kumar@freescale.com> | 2010-03-19 12:30:04 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:25 -0500 |
| commit | e590b013616a291322157d7edd39a0d10fafd57d (patch) | |
| tree | 79bdd551c0ddcb833ee3c45a89e63a70879057a5 /board | |
| parent | 6dd1a32b140e9dd0febbf5b52e1fea1fe6410e6c (diff) | |
p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz
Use a slighly larger value of CLK_CTRL for DDR at 667MHz
which fixes random crashes while linux booting.
Applicable for both NAND and NOR boot.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 3938b45c91..91486931cf 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -76,7 +76,7 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 |