diff options
| author | York Sun <yorksun@freescale.com> | 2011-01-19 15:37:33 -0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-05 10:13:50 -0600 |
| commit | 59a4089f82979d8cf24fa3ec39ea5d9cf2f42bb0 (patch) | |
| tree | 3d4befb85e4653fc8e6dcc760584b0d08efbd9c3 /board/xilinx/ml507 | |
| parent | f5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b (diff) | |
corenet_ds: pick the middle value for all tested timing parameters
For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/xilinx/ml507')
0 files changed, 0 insertions, 0 deletions