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authorwdenk <wdenk>2003-06-27 21:31:46 +0000
committerwdenk <wdenk>2003-06-27 21:31:46 +0000
commit8bde7f776c77b343aca29b8c7b58464d915ac245 (patch)
tree20f1fd99975215e7c658454a15cdb4ed4694e2d4 /board/walnut405/init.S
parent993cad9364c6b87ae429d1ed1130d8153f6f027e (diff)
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'board/walnut405/init.S')
-rw-r--r--board/walnut405/init.S68
1 files changed, 34 insertions, 34 deletions
diff --git a/board/walnut405/init.S b/board/walnut405/init.S
index d141707219d..70d029aeda8 100644
--- a/board/walnut405/init.S
+++ b/board/walnut405/init.S
@@ -46,54 +46,54 @@
#include <asm/mmu.h>
- .globl ext_bus_cntlr_init
+ .globl ext_bus_cntlr_init
ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
+ mflr r4 /* save link register */
+ bl ..getAddr
..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function */
+ /* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure all accesses to ROM are complete before changing */
/* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*------------------------------------------------------------------- */
addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
..spinlp:
- bdnz ..spinlp /* spin loop */
+ bdnz ..spinlp /* spin loop */
- /*----------------------------------------------------------------------- */
- /* Memory Bank 0 (Flash and SRAM) initialization */
- /*----------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 0 (Flash and SRAM) initialization */
+ /*----------------------------------------------------------------------- */
+ addi r4,0,pb0ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x9B01
+ ori r4,r4,0x5480
+ mtdcr ebccfgd,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr ebccfgd,r4
+ addi r4,0,pb0cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr ebccfgd,r4
- blr
+ blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
/* Description: Dummy implementation here - done in C later */
/*----------------------------------------------------------------------------- */
- .globl sdram_init
+ .globl sdram_init
sdram_init:
- blr
+ blr