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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2013-05-09 02:04:53 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2013-05-09 02:04:53 +0200
commit90f84a31dbd334e3264f4573c65f23db469571b0 (patch)
tree29f763b46ded5a3b5fe2c60124aea04cc8be3104 /board/toradex
parentf6862963315ecd20c45f71247a39c5cc30730cf6 (diff)
apalis_t30: initial integration
Add initial Apalis T30 support based off our current Colibri T30 implementation: - Updated machine ID. - USB host USBH2 and USBH3 support. Note: USBO1 support is currently broken. - Updated MMC and SD card support. - Adjusted available amount of memory.
Diffstat (limited to 'board/toradex')
-rw-r--r--board/toradex/apalis_t30/Makefile52
-rw-r--r--board/toradex/apalis_t30/apalis_t30.c24
-rw-r--r--board/toradex/apalis_t30/apalis_t30.dts152
-rw-r--r--board/toradex/apalis_t30/pinmux-config-common.h404
-rw-r--r--board/toradex/common/board.c16
-rw-r--r--board/toradex/common/tegra2_partitions.c21
6 files changed, 653 insertions, 16 deletions
diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile
new file mode 100644
index 00000000000..fadc87d2136
--- /dev/null
+++ b/board/toradex/apalis_t30/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2012
+# Toradex, Inc.
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(obj)../common)
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
new file mode 100644
index 00000000000..ebc489b3a5a
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2013
+ * Toradex, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
diff --git a/board/toradex/apalis_t30/apalis_t30.dts b/board/toradex/apalis_t30/apalis_t30.dts
new file mode 100644
index 00000000000..4004e494c82
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30.dts
@@ -0,0 +1,152 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "../../nvidia/cardhu/tegra30.dtsi"
+
+/ {
+ model = "Toradex Apalis T30";
+ compatible = "toradex,apalis_t30", "nvidia,tegra30";
+
+ config {
+ machine-arch-id = <4513>;
+ };
+
+ aliases {
+ console = "/serial@70006000";
+ usb0 = "/usb@0x7d000000";
+ usb1 = "/usb@0x7d004000";
+ usb2 = "/usb@0x7d008000";
+
+ sdmmc0 = "/sdhci@78000600";
+ sdmmc1 = "/sdhci@78000400";
+ sdmmc2 = "/sdhci@78000000";
+
+ i2c0 = "/i2c@0x7000d000";
+ i2c1 = "/i2c@0x7000c000";
+ i2c2 = "/i2c@0x7000c400";
+ i2c3 = "/i2c@0x7000c500";
+ i2c4 = "/i2c@0x7000c700";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ serial@70006000 {
+ status = "ok";
+ /*
+ * TBD - use CONFIG_SYS_PLLP_BASE_IS_408MHZ somehow here.
+ * Currently I put this back to 216MHz in fdt_decode.c
+ */
+ clock-frequency = <408000000>;
+ };
+
+ /* SD - SDMMC1 */
+ sdhci@78000000 {
+ status = "ok";
+ width = <4>; /* width of SDIO port */
+ removable = <1>;
+ /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+ cd-gpio = <&gpio 229 0>; /* card detect, gpio PCC5, SD1_CD_N */
+ };
+
+ /* MMC - SDMMC3 */
+//8-bit support broken
+ sdhci@78000400 {
+ status = "ok";
+ width = <4>; /* width of SDIO port */
+ removable = <1>;
+ /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+ cd-gpio = <&gpio 171 0>; /* card detect, gpio PV3, MMC1_CD_N */
+ };
+
+ /* Internal eMMC - SDMMC4 */
+//8-bit support broken
+ emmc: sdhci@78000600 {
+ status = "ok";
+ width = <4>; /* width of SDIO port */
+ removable = <0>;
+ };
+
+ lcd {
+ compatible = "nvidia,tegra2-lcd";
+ width = <640>;
+ height = <480>;
+ bits_per_pixel = <16>;
+ pwfm = <&pwfm0>;
+ display = <&display1>;
+ /* frame-buffer location = top of memory - carveout - fb */
+ frame-buffer = <0xbfb00000>;
+
+ pixel_clock = <25175000>;
+
+ /* Timing: ref_to_sync, sync_width, back_porch, front_porch */
+ horiz_timing = <0 96 48 16>;
+ vert_timing = <1 2 31 11>;
+
+ /* 800x480@60 (e.g. EDT ET070080DH6)
+ pixel_clock = <32460000>;
+ width = <800>;
+ height = <480>;
+ horiz_timing = <1 64 128 64>;
+ vert_timing = <1 3 22 20>;
+ */
+
+ /* 1024x768 timings
+ pixel_clock = <72000000>;
+ width = <1024>;
+ height = <768>;
+ horiz_timing = <0 136 160 24>;
+ vert_timing = <1 6 29 3>;
+ */
+
+ /* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+ backlight-enable = <&gpio 170 1>; /* PV2 - SODIMM 71: BL_ON */
+ backlight-vdd = <&gpio 255 1>;
+ lvds-shutdown = <&gpio 255 1>;
+ panel-vdd = <&gpio 255 1>;
+
+ /*
+ * Panel required timings
+ * Timing 1: delay between panel_vdd-rise and data-rise
+ * Timing 2: delay between data-rise and backlight_vdd-rise
+ * Timing 3: delay between backlight_vdd and pwm-rise
+ * Timing 4: delay between pwm-rise and backlight_en-rise
+ */
+ panel-timings = <0 0 0 0>;
+ };
+
+ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+//currently broken
+ usb@0x7d000000 {
+ status = "ok";
+ host-mode = <1>;
+ vbus-gpio = <&gpio 157 3>; /* PT5, USBO1_EN */
+ };
+
+ usbphya: usbphy@0 {
+ compatible = "smsc,usb3315";
+ status = "ok";
+ };
+
+ /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+ usb@0x7d004000 {
+ status = "ok";
+ utmi = <&usbphya>;
+ host-mode = <0>;
+ vbus-gpio = <&gpio 233 3>; /* PDD1, USBH_EN */
+ };
+
+ usbphyb: usbphy@0 {
+ compatible = "smsc,usb3315";
+ status = "ok";
+ };
+
+ /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
+ usb@0x7d008000 {
+ status = "ok";
+ utmi = <&usbphyb>;
+ host-mode = <0>;
+ };
+};
diff --git a/board/toradex/apalis_t30/pinmux-config-common.h b/board/toradex/apalis_t30/pinmux-config-common.h
new file mode 100644
index 00000000000..cc62fa41610
--- /dev/null
+++ b/board/toradex/apalis_t30/pinmux-config-common.h
@@ -0,0 +1,404 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef PINMUX_CONFIG_COMMON_H
+#define PINMUX_CONFIG_COMMON_H
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+//multiplexed KB_ROW_13
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, TRISTATE,INPUT, DISABLE, ENABLE),
+//multiplexed KB_ROW_14
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, TRISTATE,INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+//FF_RXD
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK, RSVD3, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+//multiplexed KB_ROW_10
+ DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, TRISTATE, INPUT),
+//multiplexed KB_ROW_11
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+//multiplexed KB_ROW_12
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, TRISTATE, INPUT),
+//multiplexed KB_ROW_15
+ DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV0, RSVD, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+#ifdef CONFIG_SND_HDA_CODEC_REALTEK
+ DEFAULT_PINMUX(SPDIF_IN, DAP2, DOWN, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+#ifdef CONFIG_SND_HDA_CODEC_REALTEK
+ DEFAULT_PINMUX(DAP2_FS, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, HDA, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, HDA, DOWN, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT),
+
+ /* Gpios */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ /* SDMMC1 WP gpio */
+ LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* Touch panel GPIO */
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+ LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+#if 0 // jz
+static struct pingroup_config cardhu_pinmux_e118x[] = {
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_RST_N, RSVD3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD15, NAND, UP, TRISTATE, INPUT),
+};
+
+static struct pingroup_config cardhu_pinmux_cardhu[] = {
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_RST_N, RSVD3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD15, NAND, UP, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS1_N, GMI, UP, TRISTATE, INPUT),
+ /*TP_IRQ*/
+ DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT),
+};
+
+static struct pingroup_config cardhu_pinmux_cardhu_a03[] = {
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, NAND, UP, TRISTATE, INPUT),
+};
+
+static __initdata struct tegra_pingroup_config cardhu_pinmux_e1198[] = {
+ /* SPI2 */
+ DEFAULT_PINMUX(SPI2_SCK, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_MOSI, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_MISO, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS0_N, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS2_N, SPI2, UP, NORMAL, INPUT),
+};
+#endif // jz
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* PINMUX_CONFIG_COMMON_H */
+
diff --git a/board/toradex/common/board.c b/board/toradex/common/board.c
index 46f8e0b2b98..3502d085c0f 100644
--- a/board/toradex/common/board.c
+++ b/board/toradex/common/board.c
@@ -415,7 +415,7 @@ int board_late_init(void)
unsigned char *mac_addr;
unsigned char mac_addr00[6] = {0, 0, 0, 0, 0, 0};
-#ifdef CONFIG_COLIBRI_T30
+#if defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
struct mmc *mmc;
#endif
@@ -446,7 +446,7 @@ int board_late_init(void)
ret = nand_read_skip_bad(&nand_info[0], gd->conf_blk_offset, &size,
(unsigned char *)config_block);
#endif /* CONFIG_COLIBRI_T20 */
-#ifdef CONFIG_COLIBRI_T30
+#if defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
mmc = find_mmc_device(0);
/* Just reading one 512 byte block */
ret = mmc->block_dev.block_read(0, gd->conf_blk_offset, 1, (unsigned char *)config_block);
@@ -454,7 +454,7 @@ int board_late_init(void)
ret = 0;
size = 512;
}
-#endif /* CONFIG_COLIBRI_T30 */
+#endif /* CONFIG_COLIBRI_T30 | CONFIG_APALIS_T30 */
/* Check validity */
if ((ret == 0) && (size > 0)) {
@@ -492,7 +492,7 @@ int board_late_init(void)
/* Default memory arguments */
if (!getenv("memargs")) {
-#ifndef CONFIG_COLIBRI_T30
+#if !defined(CONFIG_COLIBRI_T30) && !defined(CONFIG_APALIS_T30)
if (gd->ram_size == 0x10000000) {
/* 256 MB */
setenv("memargs", "mem=148M@0M fbmem=12M@148M nvmem=96M@160M");
@@ -500,7 +500,7 @@ int board_late_init(void)
/* 512 MB */
setenv("memargs", "mem=372M@0M fbmem=12M@372M nvmem=128M@384M");
}
-#endif /* !CONFIG_COLIBRI_T30 */
+#endif /* !CONFIG_COLIBRI_T30 && !CONFIG_APALIS_T30 */
}
/* Set eMMC or NAND kernel offset */
@@ -520,14 +520,16 @@ int board_late_init(void)
}
#endif /* CONFIG_COLIBRI_T20 */
-#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || defined(CONFIG_COLIBRI_T30)
+#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
/* Set GPT offset */
if (!getenv("gptoffset")) {
sprintf(env_str, "0x%x", (unsigned)(gd->gpt_offset));
setenv("gptoffset", env_str);
}
-#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 */
+#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 |
+ CONFIG_APALIS_T30 */
return 0;
}
diff --git a/board/toradex/common/tegra2_partitions.c b/board/toradex/common/tegra2_partitions.c
index 87b83c21ce5..7589760fbdc 100644
--- a/board/toradex/common/tegra2_partitions.c
+++ b/board/toradex/common/tegra2_partitions.c
@@ -9,7 +9,7 @@
#include <fdt_decode.h>
#include <malloc.h>
#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
- defined(CONFIG_COLIBRI_T30)
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
#include <mmc.h>
#endif
#ifdef CONFIG_COLIBRI_T20
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
static int block_size;
#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
- defined(CONFIG_COLIBRI_T30)
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
/**
* nvtegra_mmc_read - read data from mmc (unaligned)
* @param startAddress: data offset in bytes
@@ -86,7 +86,8 @@ ulong nvtegra_mmc_read(ulong startAddress, ulong dataCount, void *dst)
return dataCount;
}
-#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 */
+#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 |
+ CONFIG_APALIS_T30 */
/**
* nvtegra_print_partition_table - prints partition table info
@@ -207,7 +208,7 @@ int nvtegra_read_partition_table(nvtegra_parttable_t * pt, int boot_media)
pt_logical = 3 * 1024 * 1024 / block_size;
} else {
// 3 M - BootPartitions
-#ifdef CONFIG_COLIBRI_T30
+#if defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
pt_logical = 0x8000;
#else
pt_logical = 0x4000;
@@ -251,7 +252,7 @@ int nvtegra_read_partition_table(nvtegra_parttable_t * pt, int boot_media)
else
#endif
#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
- defined(CONFIG_COLIBRI_T30)
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
{
size = nvtegra_mmc_read(pt_offset, size, (void *)pt);
if (!size || size != sizeof(nvtegra_parttable_t)) {
@@ -260,7 +261,8 @@ int nvtegra_read_partition_table(nvtegra_parttable_t * pt, int boot_media)
return 0;
}
}
-#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 */
+#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 |
+ CONFIG_APALIS_T30 */
/* some heuristics */
p = &(pt->partinfo[0]);
@@ -460,14 +462,15 @@ void tegra_partition_init(int boot_type)
}
#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
- defined(CONFIG_COLIBRI_T30)
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
if ((pass == 1) && nvtegra_find_partition(pt, "GP1", &partinfo))
{
gd->gpt_offset =
partinfo->start_sector * block_size + 1;
DEBUG_PARTITION(partinfo);
}
-#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 */
+#endif /* (CONFIG_ENV_IS_IN_MMC & CONFIG_COLIBRI_T20) | CONFIG_COLIBRI_T30 |
+ CONFIG_APALIS_T30 */
#if DEBUG > 0
nvtegra_print_partition_table(pt);
@@ -478,7 +481,7 @@ void tegra_partition_init(int boot_type)
printf("gd->conf_blk_offset=%u\n", gd->conf_blk_offset);
printf("gd->env_offset=%u\n", gd->env_offset);
#if (defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_COLIBRI_T20)) || \
- defined(CONFIG_COLIBRI_T30)
+ defined(CONFIG_COLIBRI_T30) || defined(CONFIG_APALIS_T30)
printf("gd->gpt_offset=%u\n", gd->gpt_offset);
#endif
printf("gd->kernel_offset=%u\n", gd->kernel_offset);