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authorIgor Opaniuk <igor.opaniuk@toradex.com>2020-03-23 20:14:05 +0200
committerIgor Opaniuk <igor.opaniuk@toradex.com>2020-03-24 14:46:31 +0200
commit569703d45b63cff563822e5fec54674ed33079d2 (patch)
tree9a3c338299f6e9e9b289c56b76dd8e1bbf744588 /board/toradex/verdin-imx8mm/verdin-imx8mm.c
parent3dfa96656f746810462cf36eed76f02c1d577fb0 (diff)
verdin-imx8mm: sync with EVK board
1. MMC_UHS/HS_ enable in defconfig by default 2. VDD_DRAM/VDD_SOC changes in SPL 3. FEC anatop clock fixes Related-to: ELB-2605 Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Diffstat (limited to 'board/toradex/verdin-imx8mm/verdin-imx8mm.c')
-rw-r--r--board/toradex/verdin-imx8mm/verdin-imx8mm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 56d1490166..ff9d36661e 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -94,7 +94,7 @@ static int setup_fec(void)
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
- IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
return set_clk_enet(ENET_125MHZ);
}