diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-12-02 18:17:10 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2014-12-03 00:38:15 +0100 |
| commit | 7e8cf7a82c3ddd5b7d54a9f81cf8027b78fc0d6c (patch) | |
| tree | 8a4951aae134381e7c74d7c79f591e6679e0f502 /board/toradex/colibri_vf/colibri_vf.c | |
| parent | d7808def2faa98140e0ac9c61ec5816b65cebd56 (diff) | |
ARM: vf610: fix DIV_SELECT and clear it for USB PLL's
Fix the DIV_SELECT definition for PLL3 and PLL7, but don't set
it in the PLL control registers since USB needs a clock multiplier
of 20 to get 480MHz.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'board/toradex/colibri_vf/colibri_vf.c')
| -rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index fa027d4f75..92af6370cd 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -179,14 +179,14 @@ static void clock_init(void) CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | - ANADIG_PLL7_CTRL_POWERDOWN, ANADIG_PLL7_CTRL_ENABLE | - ANADIG_PLL7_CTRL_DIV_SELECT); + ANADIG_PLL7_CTRL_POWERDOWN | ANADIG_PLL7_CTRL_DIV_SELECT, + ANADIG_PLL7_CTRL_ENABLE); clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | ANADIG_PLL5_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | - ANADIG_PLL3_CTRL_POWERDOWN, ANADIG_PLL3_CTRL_ENABLE | - ANADIG_PLL3_CTRL_DIV_SELECT); + ANADIG_PLL3_CTRL_POWERDOWN | ANADIG_PLL3_CTRL_DIV_SELECT, + ANADIG_PLL3_CTRL_ENABLE); if (is_colibri_vf61()) { clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | |