diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-11-30 12:11:15 +0530 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-11 21:27:11 +0100 |
| commit | 4ee6eeea41c1ca6ec4255d5330fe7c7d1775eea6 (patch) | |
| tree | 37ccf5460a0ad263e6f293c7a31491d346c62aec /board/toradex/colibri_vf/colibri_vf.c | |
| parent | a589542ca5e6836d326d93d884a7d57a2119a6e1 (diff) | |
video: dcu: Add DCU support for Vybrid SoC
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Vybrid based boards too.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'board/toradex/colibri_vf/colibri_vf.c')
| -rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 7b74eb7e9d..3ba8b6b1cd 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -295,6 +295,49 @@ static void setup_iomux_gpio(void) } #endif +#ifdef CONFIG_FSL_DCU_FB +static void setup_iomux_fsl_dcu(void) +{ + static const iomux_v3_cfg_t dcu0_pads[] = { + VF610_PAD_PTE0__DCU0_HSYNC, + VF610_PAD_PTE1__DCU0_VSYNC, + VF610_PAD_PTE2__DCU0_PCLK, + VF610_PAD_PTE4__DCU0_DE, + VF610_PAD_PTE5__DCU0_R0, + VF610_PAD_PTE6__DCU0_R1, + VF610_PAD_PTE7__DCU0_R2, + VF610_PAD_PTE8__DCU0_R3, + VF610_PAD_PTE9__DCU0_R4, + VF610_PAD_PTE10__DCU0_R5, + VF610_PAD_PTE11__DCU0_R6, + VF610_PAD_PTE12__DCU0_R7, + VF610_PAD_PTE13__DCU0_G0, + VF610_PAD_PTE14__DCU0_G1, + VF610_PAD_PTE15__DCU0_G2, + VF610_PAD_PTE16__DCU0_G3, + VF610_PAD_PTE17__DCU0_G4, + VF610_PAD_PTE18__DCU0_G5, + VF610_PAD_PTE19__DCU0_G6, + VF610_PAD_PTE20__DCU0_G7, + VF610_PAD_PTE21__DCU0_B0, + VF610_PAD_PTE22__DCU0_B1, + VF610_PAD_PTE23__DCU0_B2, + VF610_PAD_PTE24__DCU0_B3, + VF610_PAD_PTE25__DCU0_B4, + VF610_PAD_PTE26__DCU0_B5, + VF610_PAD_PTE27__DCU0_B6, + VF610_PAD_PTE28__DCU0_B7, + }; + + imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads)); +} + +static void setup_tcon(void) +{ + setbits_le32(TCON0_BASE_ADDR, (1 << 29)); +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -431,6 +474,12 @@ static void clock_init(void) CCM_CSCDR3_NFC_PRE_DIV(3)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(2)); + +#ifdef CONFIG_FSL_DCU_FB + setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); + + setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); +#endif } static void mscm_init(void) @@ -469,6 +518,10 @@ int board_early_init_f(void) #ifdef CONFIG_FSL_DSPI setup_iomux_dspi(); #endif +#ifdef CONFIG_FSL_DCU_FB + setup_tcon(); + setup_iomux_fsl_dcu(); +#endif return 0; } |