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authorMarcel Ziswiler <marcel@ziswiler.com>2015-03-26 01:31:54 +0100
committerTom Warren <twarren@nvidia.com>2015-03-30 10:04:43 -0700
commite57c6e5b50d330516e30f61b824613d551316086 (patch)
treebf397ce8bf430ae712069a958e89f4c398b16db5 /board/toradex/colibri_t20/colibri_t20.c
parentd1db97aaa43d6ae5e1e790e872f79d36d8809660 (diff)
ARM: tegra: rename colibri_t20 board/configuration/device-tree
In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/toradex/colibri_t20/colibri_t20.c')
-rw-r--r--board/toradex/colibri_t20/colibri_t20.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
new file mode 100644
index 0000000000..46560948a6
--- /dev/null
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+ /* module internal USB bus to connect ethernet chipset */
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
+ /* ULPI reference clock output */
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
+ /* PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
+ /* VBus GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
+
+ /* USB 1 aka Tegra USB port 3 VBus */
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif