ARM: keystone2: Add support for getting external clock dynamically

One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

4 files changed, 110 insertions, 22 deletions

diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index cbb3077bc36..64f0c9cd5b5 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -14,12 +14,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	= 100000000,
-	[alt_core_clk]	= 100000000,
-	[pa_clk]	= 100000000,
-	[ddr3a_clk]	= 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 100000000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_800,
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 20933426b1d..6e03f6bcd02 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -14,8 +14,6 @@
 #include "mux-k2g.h"
 #include "../common/board_detect.h"
 
-#define SYS_CLK		24000000
-
 const unsigned int sysclk_array[MAX_SYSCLK] = {
 	19200000,
 	24000000,
@@ -23,13 +21,34 @@ const unsigned int sysclk_array[MAX_SYSCLK] = {
 	26000000,
 };
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	=	SYS_CLK,
-	[pa_clk]	=	SYS_CLK,
-	[tetris_clk]	=	SYS_CLK,
-	[ddr3a_clk]	=	SYS_CLK,
-	[uart_clk]	=	SYS_CLK,
-};
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+	u8 sysclk_index = get_sysclk_index();
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case pa_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case tetris_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case ddr3a_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case uart_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
 
 static int arm_speeds[DEVSPEED_NUMSPDS] = {
 	SPD400,
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index e217beaed5e..b35f24d7b58 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = {
 	[ddr3b_clk]	=	100000000,
 };
 
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 125000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 125000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3b_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_799,
 	[SPD1000]	= CORE_PLL_999,
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 2a2e0057e24..f3eea4200cb 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -14,13 +14,33 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	= 122880000,
-	[alt_core_clk]	= 100000000,
-	[pa_clk]	= 122880000,
-	[tetris_clk]	= 122880000,
-	[ddr3a_clk]	= 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 122880000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_799,